ISP1504A1ETTM STEricsson, ISP1504A1ETTM Datasheet - Page 56

• Manufacturer Part Number: ISP1504A1ETTM
• Manufacturer: STEricsson

Specifications of ISP1504A1ETTM

• Lead Free Status / RoHS Status: Compliant

Table 43.
CD00222688
Product data sheet
Bit
7 to 4
3
2
1 to 0
Symbol
-
BVALID_FALL
BVALID_RISE
-
Power Control register (address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit description
10.2 Extended register set
Addresses 00h to 3Fh of the extended register set directly map to the immediate set. This
means a read, write, set or clear operation to these extended addresses will operate on
the immediate register set.
Addresses 40h to FFh are not implemented. Operating on these addresses may result in
undefined behavior of the PHY.
Description
reserved; the link must never write logic 1 to these bits.
BValid Fall: Enables RXCMDs for HIGH-to-LOW transitions on BVALID. When BVALID changes
from HIGH to LOW, the ISP1504x1 will send an RXCMD to the link with the ALT_INT bit set to
logic 1.
This bit is optional and is not necessary for OTG devices. The session valid comparator must be
used instead.
BValid Rise: Enables RXCMDs for LOW-to-HIGH transitions on BVALID. When BVALID changes
from LOW to HIGH, the ISP1504x1 will send an RXCMD to the link with the ALT_INT bit set to
logic 1.
This bit is optional and is not necessary for OTG devices. The session valid comparator must be
used instead.
reserved; the link must never write logic 1 to this bit.
Rev. 04 — 20 May 2010
ISP1504A1; ISP1504C1
ULPI HS USB OTG transceiver
© ST-ERICSSON 2010. All rights reserved.
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