ISP1507DBS,518 NXP Semiconductors, ISP1507DBS,518 Datasheet - Page 51

• Manufacturer Part Number: ISP1507DBS,518
• Manufacturer: NXP Semiconductors

Specifications of ISP1507DBS,518

• Number Of Transceivers: 1
• Esd Protection: YeskV
• Power Supply Requirement: Single
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
Table 37.
Table 38.
Table 39.
Table 40.
ISP1507C_ISP1507D_1
Product data sheet
Bit
Symbol
Reset
Access
Bit
7 to 2
1
0
Bit
7 to 0
Bit
Symbol
Reset
Access
Symbol
SCRATCH
[7:0]
DEBUG - Debug register (address R = 15h) bit allocation
DEBUG - Debug register (address R = 15h) bit description
SCRATCH - Scratch register (address R = 16h to 18h, W = 16h, S = 17h, C = 18h) bit description
PWR_CTRL - Power Control register (address R = 3Dh to 3Fh, W = 3Dh, S = 3Eh, C = 3Fh) bit allocation
10.1.10 SCRATCH register
10.1.11 Reserved
10.1.12 Access extended register set
10.1.13 Vendor-specific registers
10.1.14 PWR_CTRL register
10.1.9 DEBUG register
R/W/S/C
Symbol
-
LINESTATE1
LINESTATE0
R
7
0
7
0
The bit allocation of the DEBUG register is given in
current value of signals useful for debugging.
Table 39
testing purposes.
Registers 19h to 2Eh are not implemented. Operating on these addresses will have no
effect on the PHY.
Address 2Fh does not contain register data. Instead it links to the extended register set.
The immediate register set maps to the lower end of the extended register set.
Addresses 30h to 3Fh contain vendor-specific registers.
Table 40
Access
R/W/S/C
R/W/S/C
R
6
0
6
0
shows the bit description of the SCRATCH register. It is an empty register for
provides the bit allocation of the PWR_CTRL register.
reserved
Value
00h
Description
reserved
Line State 1: Contains the current value of LINESTATE 1
Line State 0: Contains the current value of LINESTATE 0
R/W/S/C
R
5
0
5
0
reserved
Description
Scratch: This is an empty register byte for testing purposes. Software
can read, write, set and clear this register. The functionality of the PHY
will not be affected.
Rev. 01 — 28 May 2008
R/W/S/C
R
4
0
4
0
ULPI HS USB host and peripheral transceiver
BVALID_
R/W/S/C
FALL
R
3
0
3
0
ISP1507C; ISP1507D
Table
BVALID_
R/W/S/C
RISE
R
37. This register indicates the
2
0
2
0
reserved
R/W/S/C
STATE1
LINE
R
1
0
1
0
© NXP B.V. 2008. All rights reserved.
IGNORE_
R/W/S/C
STATE0
RESET
LINE
R
0
0
0
0
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