ISP1507DBSUM STEricsson, ISP1507DBSUM Datasheet - Page 11

• Manufacturer Part Number: ISP1507DBSUM
• Manufacturer: STEricsson

Specifications of ISP1507DBSUM

• Lead Free Status / RoHS Status: Compliant

CD00222690
Product data sheet
7.10.9.1 RESET_N
7.10.9.2 PSW_N
7.10.7 REG3V3 and REG1V8
7.10.8 XTAL1 and XTAL2
7.10.9 RESET_N/PSW_N
Regulator output voltage. These supplies are used to power the ISP1507 internal digital
and analog circuits, and must not be used to power external circuits.
For correct operation of the regulator, it is recommended that you connect REG3V3 and
REG1V8 to decoupling capacitors. For an example, see
XTAL1 is the crystal input, and XTAL2 is the crystal output. The allowed frequency on the
XTAL1 pin depends on the ISP1507 product version.
If the link requires a 60 MHz clock from the ISP1507, then either a crystal must be
attached, or a clock of the same frequency must be driven into XTAL1, with XTAL2 left
floating.
If a crystal is attached, it requires external load capacitors to GND on each terminal of the
crystal. For details, see
If at any time the system wants to stop the clock on XTAL1, the link must first put the
ISP1507 into low-power mode. The clock on XTAL1 must be restarted before low-power
mode is exited.
This pin provides two optional functions. If neither function is used, this pin must be
connected to V
An active LOW asynchronous reset pin that resets all circuits in the ISP1507. The
ISP1507 contains an internal power-on reset circuit, and therefore using the RESET_N
pin is optional. If RESET_N is not used, it must be connected to V
For details on using RESET_N, see
PSW_N is an active LOW, open-drain output pin. This pin can be connected to an active
LOW, external V
power source. An external pull-up resistor, R
pin is open-drain, allowing ganged-mode power control for multiple USB ports. For
application details, see
To use the PSW_N pin, the link must disable the reset input by setting the
IGNORE_RESET bit in the PWR_CTRL register (see
ensure that PSW_N is not misinterpreted as a reset.
If the link is in host mode, it can enable the external V
DRV_VBUS_EXT bit in the OTG_CTRL register (see
ISP1507 will drive PSW_N to LOW to enable the external V
detects an overcurrent condition (the V
external V
BUS
supply by setting DRV_VBUS_EXT to logic 0.
CC(I/O)
BUS
switch or charge pump enable circuit to control the external V
.
Section
Rev. 04 — 20 May 2010
Section
16.
16.
Section
BUS
ULPI HS USB host and peripheral transceiver
state in RXCMD is not 11b), it must disable the
9.3.2.
pullup
ISP1507C; ISP1507D
, is required when PSW_N is used. This
Section
Section
BUS
Section
power source by setting the
BUS
10.1.14) to logic 1. This will
10.1.4) to logic 1. The
power source. If the link
16.
CC(I/O)
© ST-ERICSSON 2010. All rights reserved.
.
BUS
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