ISP1507DBSUM STEricsson, ISP1507DBSUM Datasheet - Page 47

• Manufacturer Part Number: ISP1507DBSUM
• Manufacturer: STEricsson

Specifications of ISP1507DBSUM

• Lead Free Status / RoHS Status: Compliant

Table 26.
CD00222690
Product data sheet
Bit
7
6
5
4
3
2
1
0
Symbol
INTF_PROT_DIS
IND_PASSTHRU
IND_COMPL
-
CLOCK_SUSPENDM
-
3PIN_FSLS_SERIAL
6PIN_FSLS_SERIAL
INTF_CTRL - Interface Control register (address R = 07h to 09h, W = 07h, S = 08h, C = 09h) bit
description
10.1.4 OTG_CTRL register
This register controls various OTG functions of the ISP1507. The bit allocation of the
OTG_CTRL register is given in
Description
Interface Protect Disable: Controls circuitry built into the ISP1507 to protect the ULPI
when the link 3-states STP and DATA[7:0]. When this bit is enabled, the ISP1507 will
automatically detect when the link stops driving STP.
0b — Enables the interface protect circuit (default). The ISP1507 attaches a weak pull-up
resistor on STP. If STP is unexpectedly HIGH, the ISP1507 attaches weak pull-down
resistors on DATA[7:0], protecting data inputs.
1b — Disables the interface protect circuit, detaches weak pull-down resistors on
DATA[7:0], and a weak pull-up resistor on STP.
Indicator Pass-through: The ISP1507 does not support the qualification of an external
FAULT with the internal V
V
must always be set to logic 1.
0b — Not supported (default).
1b — The complement output signal is not qualified with the internal A_VBUS_VLD
comparator. The link must always set this bit to logic 1.
Indicator Complement: Informs the PHY to invert the FAULT input signal, generating the
complement output. For details, see
0b — The ISP1507 will not invert the FAULT signal (default).
1b — The ISP1507 will invert the FAULT signal.
reserved
Clock Suspend LOW: Active LOW clock suspend.
Powers down the internal clock circuitry only. By default, the clock will not be powered in
6-pin serial mode or 3-pin serial mode.
Valid only in 6-pin serial mode and 3-pin serial mode. Valid only when SUSPENDM is set to
logic 1, otherwise this bit is ignored.
0b — Clock will not be powered in 3-pin or 6-pin serial mode.
1b — Clock will be powered in 3-pin and 6-pin serial modes.
reserved
3-Pin Full-Speed Low-Speed Serial Mode: Changes the ULPI to a 3-bit serial interface.
The PHY will automatically clear this bit when 3-pin serial mode is exited.
0b — Full-speed or low-speed packets are sent using the parallel interface.
1b — Full-speed or low-speed packets are sent using the 3-pin serial interface.
6-Pin Full-Speed Low-Speed Serial Mode: Changes the ULPI to a 6-bit serial interface.
The PHY will automatically clear this bit when 6-pin serial mode is exited.
0b — Full-speed or low-speed packets are sent using the parallel interface.
1b — Full-speed or low-speed packets are sent using the 6-pin serial interface.
BUS
/FAULT pin or the V
Rev. 04 — 20 May 2010
BUS
A_VBUS_VLD
Table
power is connected to the V
27.
Section
comparator. Either a digital FAULT is input on the
ULPI HS USB host and peripheral transceiver
ISP1507C; ISP1507D
9.5.2.2.
BUS
/FAULT pin, not both. This bit
© ST-ERICSSON 2010. All rights reserved.
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