ISP1507FBS-T NXP Semiconductors, ISP1507FBS-T Datasheet - Page 14

• Manufacturer Part Number: ISP1507FBS-T
• Description: RF Transceiver USB 2.0 ULPI TRNSCVR
• Manufacturer: NXP Semiconductors

Specifications of ISP1507FBS-T

• Number Of Transceivers: 1
• Esd Protection: YeskV
• Power Supply Requirement: Single
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Compliant
• Other names: ISP1507FBS,518

NXP Semiconductors
ISP1507E_ISP1507F_1
Product data sheet
7.9.12.1 RESET_N
7.9.12.2 PSW_N
7.9.12 RESET_N/PSW_N
7.9.13 DIR
7.9.14 STP
This pin provides two optional functions. If neither function is used, this pin must be
connected to V
An active LOW asynchronous reset pin that resets all circuits in the ISP1507. The
ISP1507 contains an internal power-on reset circuit, and therefore using the RESET_N
pin is optional. If RESET_N is not used, it must be connected to V
For details on using RESET_N, see
PSW_N is an active LOW, open-drain output pin. This pin can be connected to an active
LOW, external V
power source. An external pull-up resistor, R
pin is open-drain, allowing ganged-mode power control for multiple USB ports. For
application details, see
To use the PSW_N pin, the link must disable the reset input by setting the
IGNORE_RESET bit in the PWR_CTRL register (see
ensure that PSW_N is not misinterpreted as a reset.
If the link is in host mode, it can enable the external V
DRV_VBUS_EXT bit in the OTG_CTRL register (see
ISP1507 will drive PSW_N to LOW to enable the external V
detects an overcurrent condition (the V
external V
ULPI direction output pin. Controls the direction of the data bus. By default, the ISP1507
holds DIR at LOW, causing the data bus to be an input. When DIR is LOW, the ISP1507
listens for data from the link. The ISP1507 pulls DIR to HIGH only when it has data to
send to the link, which is for one of two reasons:
For details on DIR usage, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 .
ULPI stop input pin. The link must assert STP to signal the end of a USB transmit packet
or a register write operation. When DIR is asserted, the link can optionally assert STP to
abort the ISP1507, causing it to deassert DIR in the next clock cycle. A weak pull-up
resistor is incorporated into the STP pin as part of the interface protect feature. For details,
see
For details on STP usage, refer to UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1 .
•
•
To send the USB receive data, RXCMD status updates and register reads data to the
link.
To block the link from driving the data bus during power-up, reset and low-power
mode (suspend).
Section
BUS
9.3.1.
supply by setting DRV_VBUS_EXT to logic 0.
CC(I/O)
BUS
switch or charge pump enable circuit to control the external V
.
Section
Rev. 01 — 28 May 2008
16.
Section
BUS
state in RXCMD is not 11b), it must disable the
9.3.2.
pullup
ISP1507E; ISP1507F
, is required when PSW_N is used. This
Section
Section
BUS
ULPI HS USB OTG transceiver
power source by setting the
BUS
10.1.4) to logic 1. The
10.1.14) to logic 1. This will
power source. If the link
CC(I/O)
© NXP B.V. 2008. All rights reserved.
.
BUS
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