ISP1507FBS-T NXP Semiconductors, ISP1507FBS-T Datasheet - Page 52

• Manufacturer Part Number: ISP1507FBS-T
• Description: RF Transceiver USB 2.0 ULPI TRNSCVR
• Manufacturer: NXP Semiconductors

Specifications of ISP1507FBS-T

• Number Of Transceivers: 1
• Esd Protection: YeskV
• Power Supply Requirement: Single
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Compliant
• Other names: ISP1507FBS,518

NXP Semiconductors
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
ISP1507E_ISP1507F_1
Product data sheet
Bit
Symbol
Reset
Access
Bit
7 to 5
4
3
2
1
0
Bit
Symbol
Reset
Access
Bit
7 to 2
1
0
Bit
7 to 0
Symbol
reserved
ID_GND_L
SESS_END_L
SESS_VALID_L
VBUS_VALID_L
HOST_DISCON_L
Symbol
SCRATCH[7:0]
USB_INTR_L - USB Interrupt Latch register (address R = 14h) bit allocation
USB_INTR_L - USB Interrupt Latch register (address R = 14h) bit description
DEBUG - Debug register (address R = 15h) bit allocation
DEBUG - Debug register (address R = 15h) bit description
SCRATCH - Scratch register (address R = 16h to 18h, W = 16h, S = 17h, C = 18h) bit description
10.1.10 SCRATCH register
10.1.9 DEBUG register
Symbol
-
LINESTATE1
LINESTATE0
R
R
7
0
7
0
The bit allocation of the DEBUG register is given in
current value of signals useful for debugging.
Table 40
testing purposes.
Access
R/W/S/C
reserved
Description
-
ID Ground Latch: Automatically set when an unmasked event occurs on ID_GND. Cleared
when this register is read.
Session End Latch: Automatically set when an unmasked event occurs on SESS_END.
Cleared when this register is read.
Session Valid Latch: Automatically set when an unmasked event occurs on SESS_VLD.
Cleared when this register is read.
V
Cleared when this register is read.
Host Disconnect Latch: Automatically set when an unmasked event occurs on
HOST_DISCON. Cleared when this register is read.
BUS
R
R
6
0
6
0
shows the bit description of the SCRATCH register. It is an empty register for
Valid Latch: Automatically set when an unmasked event occurs on VBUS_VLD.
Description
reserved
Line State 1: Contains the current value of LINESTATE 1
Line State 0: Contains the current value of LINESTATE 0
Value
00h
R
R
5
0
5
0
reserved
Rev. 01 — 28 May 2008
Description
Scratch: This is an empty register byte for testing purposes. Software
can read, write, set and clear this register. The functionality of the PHY
will not be affected.
ID_GND_L
R
R
4
0
4
0
SESS_
END_L
R
R
3
0
3
0
ISP1507E; ISP1507F
Table
VALID_L
SESS_
ULPI HS USB OTG transceiver
R
R
2
0
38. This register indicates the
2
0
VALID_L
STATE1
VBUS_
LINE
R
R
1
0
1
0
© NXP B.V. 2008. All rights reserved.
DISCON_L
STATE0
HOST_
LINE
R
R
0
0
0
0
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