SAA7104H/V1,518 NXP Semiconductors, SAA7104H/V1,518 Datasheet - Page 18

• Manufacturer Part Number: SAA7104H/V1,518
• Manufacturer: NXP Semiconductors

Specifications of SAA7104H/V1,518

• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
7.18
The I
supporting 7-bit slave addresses and 400 kbits/s
guaranteed transfer rate. It uses 8-bit subaddressing with
an auto-increment function. All registers are write and
read, except two read only status bytes.
The register bit map consists of an RGB Look-Up Table
(LUT), a cursor bit map and control registers. The LUT
contains three banks of 256 bytes, where each RGB triplet
is assigned to one address. Thus a write access needs the
LUT address and three data bytes following subaddress
FFH. For further write access auto-incrementing of the
LUT address is performed. The cursor bit map access is
similar to the LUT access but contains only a single byte
per address.
The I
7.19
In order to reduce the power consumption, the SAA7104H;
SAA7105H supports 2 power-down modes, accessible via
the I
turns off the digital-to-analog converters and the pixel
clock synthesizer. The digital power-down mode turns off
all internal clocks and sets the digital outputs to LOW
except the I
programming and can still be accessed in this mode,
however not all registers can be read or written to. Reading
or writing to the look-up tables, the cursor and the HD sync
generator require a valid pixel clock. The typical supply
current in full power-down is approximately 5 mA.
2004 Mar 04
14 24 00 00
54 00 00 00
Write to subaddress D3H (no signals are directed to pins HSM_CSYNC and VSM)
00
CC 00
80 00
0A 00
CC 00
80 00
Write to subaddress DCH
0B
Digital video encoder
2
2
2
C-bus. The analog power-down mode (DOWNA = 1)
C-bus interface is a standard slave transceiver,
C-bus slave address is defined as 88H.
I
Power-down modes
SEQUENCE
2
C-bus interface
2
C-bus interface. The IC keeps its
use pattern entries 4, 1, 4 and 2 in this sequence (for sync-black-sync-black-null)
use pattern entries 4 and 5 in this sequence (for sync-black)
points to first entry of value array (index 0)
black level, to be added during active video
sync level LOW (minimum output voltage)
sync level HIGH (3-level sync)
black level (needed elsewhere)
null (identical to sync level LOW)
insertion is active, gain for signal is adapted accordingly
18
Because the analog power-down mode turns off the pixel
clock synthesizer, there are limitations in some
applications. If there is no pixel clock, the IC is not able to
set its outputs to LOW. So, in most cases, DOWNA and
DOWND should be set to logic 1 simultaneously. If the
EIDIV bit is logic 1, it should be set to logic 0 before
power-down.
7.20
The SAA7104H; SAA7105H needs to provide a
continuous data stream at its analog outputs as well as
receive a continuous stream of data from its data source.
Because there is no frame memory isolating the data
streams, restrictions apply to the input frame timings.
Input and output processing of the SAA7104H; SAA7105H
are only coupled through the vertical frequencies. In
master mode, the encoder provides a vertical sync and an
odd/even pulse to the input processing. In slave mode, the
encoder receives them.
The parameters of the input field are mainly given by the
memory capacity of the SAA7104H; SAA7105H. The rule
is that the scaler and thus the input processing needs to
provide the video data in the same time frames as the
encoder reads them. Therefore, the vertical active video
times (and the vertical frequencies) need to be the same.
The second rule is that there has to be data in the buffer
FIFO when the encoder enters the active video area.
Therefore, the vertical offset in the input path needs to be
a bit shorter than the offset of the encoder.
COMMENT
Programming the SAA7104H; SAA7105H
SAA7104H; SAA7105H
Product specification