M368L3223HUS-CCC Samsung Semiconductor, M368L3223HUS-CCC Datasheet - Page 17

• Manufacturer Part Number: M368L3223HUS-CCC
• Manufacturer: Samsung Semiconductor

Specifications of M368L3223HUS-CCC

• Lead Free Status / RoHS Status: Compliant

15.0 System Notes:
a. Pullup slew rate is characteristized under the test conditions as shown in Figure 2.
b. Pulldown slew rate is measured under the test conditions shown in Figure 3.
c. Pullup slew rate is measured between (V
d. Evaluation conditions
e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range.
f. Verified under typical conditions for qualification purposes.
g. TSOPII package divices only.
h. Only intended for operation up to 266 Mbps per pin.
i. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5V/ns as shown in Table 2. The Input slew rate is
j. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables 3 & 4. Input slew rate
k. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser on the lesser of
l. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi tions through the DC
256MB, 512MB Unbuffered DIMM
For example : If Slew Rate 1 is 0.5 V/ns and slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is - 0.5ns/V . Using the table given, this
would result in the need for an increase in tDS and tDH of 100 ps.
Pulldown slew rate is measured between (V
Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output switching.
Example : For typical slew rate, DQ0 is switching
Typical
Minimum : 70 °C (T Ambient), V
Maximum : 0 °C (T Ambient), V
For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation.
based on the lesser of the slew rates detemined by either V
is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, Input slew rate is based on the lesser of the slew rates determined by either
V
the AC - AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew rates deter mined by either V
or V
region must be monotonic.
IH
(AC) to V
IH
(DC) to V
: 25 °C (T Ambient), V
For minmum slew rate, all DQ bits are switching from either high to low, or low to high.
The remaining DQ bits remain the same as for previous state.
IL
(AC) or V
IL
(DC), and similarly for rising transitions.
IH
(DC) to V
DDQ
DDQ
DDQ
IL
= 2.5V(for DDR266/333) and 2.6V(for DDR400), typical process
= 2.3V(for DDR266/333) and 2.5V(for DDR400), slow - slow process
= 2.7V(for DDR266/333) and 2.7V(for DDR400), fast - fast process
(DC), similarly for rising transitions. The delta rise/fall rate is calculated as: {1/(Slew Rate1)} - {1/(Slew Rate2)}
DDQ
DDQ
/2 - 320 mV +/- 250 mV)
/2 + 320 mV +/- 250 mV)
Output
Output
Figure 3 : Pulldown slew rate test load
Figure 2 : Pullup slew rate test load
IH
(AC) to V
V
V
15 of 20
SSQ
DDQ
IL
(AC) or V
50
50
Ω
Ω
Test point
Test point
IH
(DC) to V
IL
(DC), similarly for rising transitions.
Rev. 1.01 August 2008
DDR SDRAM
IH
(AC) to V
IL
(AC)