M368L3223HUS-CCC Samsung Semiconductor, M368L3223HUS-CCC Datasheet - Page 4

• Manufacturer Part Number: M368L3223HUS-CCC
• Manufacturer: Samsung Semiconductor

Specifications of M368L3223HUS-CCC

• Lead Free Status / RoHS Status: Compliant

1.0 Ordering Information
2.0 Operating Frequencies
3.0 Feature
• V
• V
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [DQ] (x4,x8) & [L(U)DQS] (x16)
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency : DDR333(2.5 Clock), DDR400(3 Clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
• Serial presence detect with EEPROM
• PCB : Height 1,250 (mil) & single (128MB, 256MB), double (512GB) sided
• SSTL_2 Interface
•
•
256MB, 512MB Unbuffered DIMM
66pin TSOP II
RoHS compliant
DD
DD
: 2.5V ± 0.2V, V
: 2.6V ± 0.1V, V
M381L3223HUM-C(L)CC/B3
M381L6423HUM-C(L)CC/B3
M368L3223HUS-C(L)CC/B3
M368L6423HUN-C(L)CC/B3
Speed @CL2.5
CL-tRCD-tRP
Speed @CL2
Speed @CL3
Part Number
Lead-Free
DDQ
DDQ
184Pin Unbuffered DIMM based on 256Mb H-die (x8)
: 2.5V ± 0.2V for DDR333
: 2.6V ± 0.1V for DDR400
package
Density
256MB
512MB
CC(DDR400@CL=3)
166MHz
200MHz
3-3-3
-
Organization
2 of 20
32M x 64
32M x 72
64M x 64
64M x 72
32Mx8 (K4H560838H) * 8EA
32Mx8 (K4H560838H) * 9EA
32Mx8 (K4H560838H) * 16EA
32Mx8 (K4H560838H) * 18EA
Component Composition
Rev. 1.01 August 2008
B3(DDR333@CL=2.5)
133MHz
166MHz
2.5-3-3
-
DDR SDRAM
1,250mil
1,250mil
1,250mil
1,250mil
Height