M368L3223HUS-CCC Samsung Semiconductor, M368L3223HUS-CCC Datasheet - Page 18

• Manufacturer Part Number: M368L3223HUS-CCC
• Manufacturer: Samsung Semiconductor

Specifications of M368L3223HUS-CCC

• Lead Free Status / RoHS Status: Compliant

16.0 Command Truth Table
Note :
1. OP Code : Operand Code. A
2. EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS.
3. Auto refresh functions are same as the CBR refresh of DRAM.
4. BA
5. If A
6. During burst write with auto precharge, new read/write command can not be issued.
7. Burst stop command is valid at every burst length.
8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).
9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
256MB, 512MB Unbuffered DIMM
Precharge Power Down Mode
Column Address
Column Address
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
If both BA
If BA
If BA
If both BA
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at t
Precharge
0
10
Register
Register
Refresh
Read &
Write &
~ BA
0
0
Active Power Down
No operation (NOP) : Not defined
/AP is "High" at row precharge, BA
is "High" and BA
is "Low" and BA
1
Bank Active & Row Addr.
0
0
: Bank select addresses.
and BA
and BA
COMMAND
Burst Stop
1
1
are "Low" at read, write, row active and precharge, bank A is selected.
are "High" at read, write, row active and precharge, bank D is selected.
Auto Precharge Disable
Auto Precharge Disable
DM
Auto Precharge Enable
Auto Precharge Enable
1
1
Refresh
is "High" at read, write, row active and precharge, bank C is selected.
is "Low" at read, write, row active and precharge, bank B is selected.
Mode Register Set
Self
Extended MRS
Bank Selection
Auto Refresh
All Banks
0
~ A
12
& BA
Entry
Entry
Entry
0
Exit
Exit
Exit
and BA
0
~ BA
1
1
are ignored and all banks are selected.
CKEn-1
: Program keys. (@EMRS/MRS)
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
RP
after the end of burst.
CKEn
H
H
H
H
X
X
X
X
X
X
X
X
L
L
L
16 of 20
CS
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
X
L
L
L
RAS
X
H
X
H
H
H
X
V
X
X
H
X
V
X
H
L
L
L
L
L
(V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)
CAS
H
H
H
H
H
H
L
L
L
X
L
L
X
V
X
X
X
V
X
WE BA0,1 A10/AP
H
H
X
H
H
X
V
X
X
H
X
V
X
H
L
L
L
L
L
Rev. 1.01 August 2008
V
V
V
V
X
(A0~A9, A11,A12)
OP CODE
OP CODE
H
H
H
Row Address
L
L
L
DDR SDRAM
X
X
X
X
X
X
X
A11, A12
Address
Address
A0 ~ A9
Column
Column
X
Note
1, 2
1, 2
4, 6
3
3
3
3
4
4
4
7
5
8
9
9