MT9HTF6472PY-667F1 Micron Technology Inc, MT9HTF6472PY-667F1 Datasheet - Page 14

• Manufacturer Part Number: MT9HTF6472PY-667F1
• Manufacturer: Micron Technology Inc

Specifications of MT9HTF6472PY-667F1

• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 240RDIMM
• Device Core Size: 72b
• Organization: 64Mx72
• Total Density: 512MByte
• Chip Density: 512Mb
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 1.62A
• Number Of Elements: 9
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 240
• Mounting: Socket
• Lead Free Status / RoHS Status: Compliant

Table 11: DDR2 I
Values shown for MT47H64M8 DDR2 SDRAM only and are computed from values specified in the 512Mb (64 Meg x 8)
component data sheet
PDF: 09005aef82250868
htf9c32_64_128x72.pdf - Rev. F 3/10 EN
Parameter
Operating one bank active-precharge current:
t
commands; Address bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
4, CL = CL (I
(I
Address bus inputs are switching; Data pattern is same as I
Precharge power-down current: All device banks idle;
CKE is LOW; Other control and address bus inputs are stable; Data bus
inputs are floating
Precharge quiet standby current: All device banks idle;
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;
Data bus inputs are floating
Precharge standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are switching; Da-
ta bus inputs are switching
Active power-down current: All device banks open;
=
puts are stable; Data bus inputs are floating
Active standby current: All device banks open;
t
mands; Other control and address bus inputs are switching; Data bus
inputs are switching
Operating burst write current: All device banks open; Continuous
burst writes; BL = 4, CL = CL (I
(I
Address bus inputs are switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst
read, I
MAX (I
mands; Address bus inputs are switching; Data bus inputs are switching
Burst refresh current:
(I
trol and address bus inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
RC (I
RAS MAX (I
DD
DD
DD
t
CK (I
),
),
) interval; CKE is HIGH, S# is HIGH between valid commands; Other con-
DD
t
t
RCD =
RP =
OUT
DD
DD
),
),
t
); CKE is LOW; Other control and address bus in-
RAS =
= 0mA; BL = 4, CL = CL (I
t
t
DD
RP (I
RP =
DD
t
RCD (I
), AL = 0;
),
t
DD
t
RP =
t
RAS MIN (I
RP (I
); CKE is HIGH, S# is HIGH between valid commands;
DD
DD
t
DD
); CKE is HIGH, S# is HIGH between valid commands;
RP (I
Specifications and Conditions – 512MB
t
CK =
t
); CKE is HIGH, S# is HIGH between valid com-
CK =
DD
DD
); CKE is HIGH, S# is HIGH between valid com-
t
DD
CK (I
t
); CKE is HIGH, S# is HIGH between valid
256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
CK (I
), AL = 0;
DD
DD
DD
),
), AL = 0;
); REFRESH command at every
t
RC =
t
CK =
t
RC (I
t
CK =
t
CK (I
DD
t
CK =
t
CK =
),
t
t
DD
CK (I
CK =
t
RAS =
),
t
CK
t
CK (I
t
t
RAS =
DD
CK (I
t
OUT
CK =
t
DD4W
t
CK (I
CK =
),
14
Fast PDN exit
MR[12] = 0
Slow PDN ex-
it MR[12] = 1
t
DD
RAS MIN
t
= 0mA; BL =
DD
RAS =
),
t
DD
t
CK (I
RAS MAX
),
t
t
CK (I
); CKE is
RAS =
t
RC =
t
RFC
t
DD
RAS
DD
Micron Technology, Inc. reserves the right to change products or specifications without notice.
);
);
Symbol
I
I
I
I
I
I
I
DD4W
I
I
DD2Q
DD2N
DD3N
I
I
DD2P
DD3P
DD4R
DD0
DD1
DD5
DD6
-80E/
1035
1755
1845
2070
800
900
450
495
360
108
630
63
63
1530
1620
1620
-667
© 2003 Micron Technology, Inc. All rights reserved.
810
945
405
450
315
108
585
63
63
I
DD
-53E
1260
1305
1530
Specifications
720
855
360
405
270
108
495
63
63
1035
1035
1485
-40E
720
810
315
360
225
108
405
63
63
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA