MT9HTF6472PY-667F1 Micron Technology Inc, MT9HTF6472PY-667F1 Datasheet - Page 16

• Manufacturer Part Number: MT9HTF6472PY-667F1
• Manufacturer: Micron Technology Inc

Specifications of MT9HTF6472PY-667F1

• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 240RDIMM
• Device Core Size: 72b
• Organization: 64Mx72
• Total Density: 512MByte
• Chip Density: 512Mb
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 1.62A
• Number Of Elements: 9
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 240
• Mounting: Socket
• Lead Free Status / RoHS Status: Compliant

Table 12: DDR2 I
Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) com-
ponent data sheet
PDF: 09005aef82250868
htf9c32_64_128x72.pdf - Rev. F 3/10 EN
Parameter
Operating one bank active-precharge current:
t
commands; Address bus inputs are switching; Data bus inputs are switch-
ing
Operating one bank active-read-precharge current: I
= 4, CL = CL (I
(I
mands; Address bus inputs are switching; Data pattern is same as I
Precharge power-down current: All device banks idle;
CKE is LOW; Other control and address bus inputs are stable; Data bus
inputs are floating
Precharge quiet standby current: All device banks idle;
(I
stable; Data bus inputs are floating
Precharge standby current: All device banks idle;
is HIGH, S# is HIGH; Other control and address bus inputs are switching;
Data bus inputs are switching
Active power-down current: All device banks open;
t
bus inputs are stable; Data bus inputs are floating
Active standby current: All device banks open;
t
commands; Other control and address bus inputs are switching; Data
bus inputs are switching
Operating burst write current: All device banks open; Continuous
burst writes; BL = 4, CL = CL (I
MAX (I
mands; Address bus inputs are switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous
burst read, I
=
commands; Address bus inputs are switching; Data bus inputs are switch-
ing
Burst refresh current:
(I
control and address bus inputs are switching; Data bus inputs are switch-
ing
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
RC (I
CK =
RAS MAX (I
DD
DD
DD
t
RAS MAX (I
),
); CKE is HIGH, S# is HIGH; Other control and address bus inputs are
) interval; CKE is HIGH, S# is HIGH between valid commands; Other
DD
t
t
RCD =
CK (I
DD
),
),
t
RAS =
DD
t
RP =
DD
OUT
t
DD
RCD (I
); CKE is LOW; Other control and address
DD
),
), AL = 0;
= 0mA; BL = 4, CL = CL (I
t
),
t
t
RP =
RAS MIN (I
RP (I
t
RP =
DD
DD
DD
); CKE is HIGH, S# is HIGH between valid com-
t
RP (I
Specifications and Conditions (Die Revision A) – 1GB
t
t
); CKE is HIGH, S# is HIGH between valid com-
RP (I
CK =
t
CK =
DD
DD
DD
); CKE is HIGH, S# is HIGH between valid
DD
t
); CKE is HIGH, S# is HIGH between valid
256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
CK (I
t
); CKE is HIGH, S# is HIGH between valid
CK (I
), AL = 0;
DD
DD
); REFRESH command at every
),
DD
t
RC =
t
CK =
), AL = 0;
t
RC (I
t
CK (I
t
CK =
t
DD
CK =
t
t
DD
CK =
CK =
),
),
t
t
CK (I
RAS =
t
t
RAS =
CK (I
t
t
OUT
CK =
t
CK (I
t
CK (I
Fast PDN exit
MR[12] = 0
Slow PDN ex-
it MR[12] = 1
CK =
16
DD
= 0mA; BL
DD
t
DD
),
RAS MIN
t
DD
t
CK (I
RAS
),
t
t
CK
),
); CKE
RAS =
DD4W
t
RC =
t
t
RAS
RFC
DD
Micron Technology, Inc. reserves the right to change products or specifications without notice.
);
Symbol
I
I
I
I
I
I
I
DD4W
DD2Q
I
I
DD2N
DD3N
DD4R
I
I
DD2P
DD3P
DD0
DD1
DD5
DD6
-80E/
1665
1710
2520
800
900
990
585
630
405
126
675
63
63
1440
1440
2340
-667
810
900
495
540
360
126
630
63
63
© 2003 Micron Technology, Inc. All rights reserved.
I
DD
1170
1305
2250
-53E
720
855
369
405
315
126
495
Specifications
63
63
1980
-40E
630
720
315
360
315
126
405
990
990
63
63
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA