LSI53CF92A-64QFP LSI, LSI53CF92A-64QFP Datasheet - Page 114

• Manufacturer Part Number: LSI53CF92A-64QFP
• Manufacturer: LSI

Specifications of LSI53CF92A-64QFP

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 5.16
5.5.12 Target Abort DMA
5-22
Sequence Step
0 0 1
0 0 1
0 1 0
0 1 0
[2:0]
Target Receive Command Sequence
Interrupt Register
0 0 0 0 1 0 0 0
0 0 0 1 1 0 0 0
0 0 0 0 1 0 0 0
0 0 0 1 1 0 0 0
Table 5.16
The Target Abort DMA command allows the microprocessor to stop a
target data transfer command whose progress has been halted due to
inactivity on the DMA channel. One potential application is a system
containing a microprocessor and an intelligent buffer controller that
handles buffer management. The microprocessor sets up the buffer
controller and overprograms the transfer counter prior to issuing a SCSI
transfer command to the chip. When the buffer controller runs out of
buffers, it interrupts the microprocessor. The microprocessor stops the
chip and commands it to disconnect from the SCSI bus.
The abort DMA command executes from the top of the command FIFO.
If there is a stacked command waiting to execute, it is overwritten and
the Gross Error bit 6
clears itself from the command stack after being decoded.
The abort DMA command can only be used when all of the following
conditions are true:
Command Set
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Either the Target Send Data or Target Receive Data command is
operating
The DMA controller has halted
[7:0]
Note:
lists the Target Receive Command sequence.
The Target Abort DMA command should be used with
extreme caution. Before using this command, verify that the
removal of DREQ by this command does not confuse the
system’s DMA controller.
Interpretation
Stopped during command transfer due to parity error; check
FIFO flags.
Stopped during command transfer due to parity error; ATN/
asserted by initiator.
Received entire command descriptor block.
Received entire CDB; initiator asserted ATN/.
(Status
register) is set. The abort DMA command