LSI53CF92A-64QFP LSI, LSI53CF92A-64QFP Datasheet - Page 24

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LSI53CF92A-64QFP

Manufacturer Part Number
LSI53CF92A-64QFP
Description
Manufacturer
LSI
Datasheet

Specifications of LSI53CF92A-64QFP

Lead Free Status / RoHS Status
Supplier Unconfirmed
2.2.1 Bus-Initiated Selection
2-4
to determine if the FSC selected another device, or if it was selected by
another device. The former case causes a Function Complete Interrupt,
the latter case causes a Selection or Reselection interrupt.
When the FSC has been selected as a target, the following data is in
its FIFO:
The bus ID is always present and is always one byte. It is an unencoded
version of the state of the bus during Selection phase. Any SCSI data bits
that were true during Selection phase are set. The target ID must always
be set. In arbitrating systems, the initiator ID must also be set. The
initiator ID is optional in nonarbitrating systems. If parity checking is
enabled, parity must be valid during the bus-initiated selection. If parity is
not valid, the FSC does not respond to bus-initiated selection.
The identify message, if sent, is also be placed in the FIFO. The identify
message is optional in SCSI-1 systems but is always one byte if it is
used. In SCSI-2 systems a one or three byte message is sent, consisting
of the one-byte identify message and an optional two-byte command
queuing message. If the FSC is selected with ATN/ false, it stores a null
byte (00) in the FIFO behind the bus ID, then begins requesting
command phase bytes. A detected parity error causes the FSC to
interrupt and stop, if parity checking is enabled.
If the FSC is selected with ATN/ true and the SCSI-2 bit is not set, it
requests one message byte and places it in the FIFO behind the bus ID.
Then it requests Command phase bytes unless the message byte is not
a valid identify message, bit 7 in the
is not set, or a parity error is detected, which causes the FSC to interrupt
and stop. The Sequence Step register can then be examined to
determine what events have been completed.
Functional Description
Copyright © 1995–2002 by LSI Logic Corporation. All rights reserved.
Bus ID
Identify message
Optional two-byte command queuing message
Command Descriptor Block (CDB)
Configuration 3 (Config 3)
register

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