82V3355DKG IDT, Integrated Device Technology Inc, 82V3355DKG Datasheet - Page 84

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82V3355DKG

Manufacturer Part Number
82V3355DKG
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet

Specifications of 82V3355DKG

Function
Wan PLL
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Package Type
TQFP
Pin Count
64
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
IN3_CMOS_STS - CMOS Input Clock 3 Status
Programming Information
Address: 47H
Type: Read
Default Value: XXXXX110
IDT82V3355
7 - 3
Bit
2
1
0
7
-
IN3_CMOS_NO_ACTIVITY_ALARM
IN3_CMOS_FREQ_HARD_ALARM
IN3_CMOS_PH_LOCK_ALARM
6
-
Name
-
5
-
Reserved.
This bit indicates whether IN3_CMOS is in frequency hard alarm status.
0: No frequency hard alarm.
1: In frequency hard alarm status. (default)
This bit indicates whether IN3_CMOS is in no-activity alarm status.
0: No no-activity alarm.
1: In no-activity alarm status. (default)
This bit indicates whether IN3_CMOS is in phase lock alarm status.
0: No phase lock alarm. (default)
1: In phase lock alarm status.
If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘0’, this bit is cleared by writing ‘1’ to this bit; if the
PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, this bit is cleared after a period (= TIME_OUT_VALUE[5:0] (b5~0,
08H) X MULTI_FACTOR[1:0] (b7~6, 08H) in second) which starts from when the alarm is raised.
4
-
84
3
-
IN3_CMOS_FRE
Q_HARD_ALAR
Description
M
2
SYNCHRONOUS ETHERNET WAN PLL
IN3_CMOS_NO_
ACTIVITY_ALAR
M
1
IN3_CMOS_PH_
LOCK_ALARM
March 3, 2009
0

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