82V3355DKG IDT, Integrated Device Technology Inc, 82V3355DKG Datasheet - Page 95
82V3355DKG
Manufacturer Part Number
82V3355DKG
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.82V3355DKG.pdf
(129 pages)
Specifications of 82V3355DKG
Function
Wan PLL
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Package Type
TQFP
Pin Count
64
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
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PHASE_LOSS_COARSE_LIMIT_CNFG - Phase Loss Coarse Detector Limit Configuration *
Programming Information
IDT82V3355
Address: 5AH
Type: Read / Write
Default Value: 10000101
3 - 0 PH_LOS_COARSE_LIMT[3:0]
Bit
7
6
5
4
COARSE_PH_L
OS_LIMT_EN
COARSE_PH_LOS_LIMT_EN
MULTI_PH_8K_4K_2K_EN
7
MULTI_PH_APP
WIDE_EN
Name
WIDE_EN
6
This bit controls whether the occurrence of the coarse phase loss will result in the T0/T4 DPLL unlocked.
0: Disabled.
1: Enabled. (default)
Refer to the description of the MULTI_PH_8K_4K_2K_EN bit (b4, 5AH).
This bit determines whether the PFD output of T0/T4 DPLL is limited to ±1 UI or is limited to the coarse phase limit.
0: Limited to ±1 UI. (default)
1: Limited to the coarse phase limit. When the selected input clock is of 2 kHz, 4 kHz or 8 kHz, the coarse phase limit depends
on the MULTI_PH_8K_4K_2K_EN bit, the WIDE_EN bit and the PH_LOS_COARSE_LIMT[3:0] bits; when the selected input
clock is of other frequencies but 2 kHz, 4 kHz and 8 kHz, the coarse phase limit depends on the WIDE_EN bit and the
PH_LOS_COARSE_LIMT[3:0] bits. Refer to the description of the MULTI_PH_8K_4K_2K_EN bit (b4, 5AH) for details.
This bit, together with the WIDE_EN bit (b6, 5AH) and the PH_LOS_COARSE_LIMT[3:0] bits (b3~0, 5AH), determines the
coarse phase limit when the selected input clock is of 2 kHz, 4 kHz or 8 kHz. When the selected input clock is of other frequen-
cies but 2 kHz, 4 kHz and 8 kHz, the coarse phase limit depends on the WIDE_EN bit and the PH_LOS_COARSE_LIMT[3:0]
bits.
These bit set the coarse phase limit. The limit is used only in some cases. Refer to the description of the
MULTI_PH_8K_4K_2K_EN bit (b4, 5AH).
0000: ±1 UI.
0001: ±3 UI.
0010: ±7 UI.
0011: ±15 UI.
0100: ±31 UI.
0101: ±63 UI. (default)
0110: ±127 UI.
0111: ±255 UI.
1000: ±511 UI.
1001: ±1023 UI (T0); Reserved (T4).
1010-1111: Reserved.
MULTI_PH_APP
Selected Input Clock MULTI_PH_8K_4K_2K_EN WIDE_EN
2 kHz, 4 kHz or 8 kHz
other than 2 kHz, 4
kHz and 8 kHz
5
MULTI_PH_8K_
4K_2K_EN
4
don’t-care
95
0
1
PH_LOS_COA
RSE_LIMT3
3
Description
don’t-care
0
1
0
1
PH_LOS_COA
RSE_LIMT2
set by the PH_LOS_COARSE_LIMT[3:0] bits
set by the PH_LOS_COARSE_LIMT[3:0] bits
2
SYNCHRONOUS ETHERNET WAN PLL
Coarse Phase Limit
PH_LOS_COA
RSE_LIMT1
(b3~0, 5AH).
(b3~0, 5AH).
±1 UI
±1 UI
±1 UI
1
PH_LOS_COA
March 3, 2009
RSE_LIMT0
0
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