SSTUA32866EC/G-T NXP Semiconductors, SSTUA32866EC/G-T Datasheet - Page 3

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SSTUA32866EC/G-T

Manufacturer Part Number
SSTUA32866EC/G-T
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of SSTUA32866EC/G-T

Logic Family
SSTU
Logical Function
Registered Buffer
Number Of Elements
1
Number Of Bits
25
Number Of Inputs
25
Number Of Outputs
25
High Level Output Current
-8mA
Low Level Output Current
8mA
Propagation Delay Time
3ns
Operating Supply Voltage (typ)
1.8V
Operating Supply Voltage (max)
2V
Operating Supply Voltage (min)
1.7V
Clock-edge Trigger Type
Posit/Negat-Edge
Polarity
Non-Inverting
Technology
CMOS
Frequency (max)
450(Min)MHz
Mounting
Surface Mount
Pin Count
96
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Compliant
NXP Semiconductors
SSTUA32866_2
Product data sheet
Fig 2. Parity logic diagram for 1 : 2 Register A configuration (positive logic); C0 = 0, C1 = 1
D2, D3, D5, D6,
D8 to D14
PAR_IN
RESET
VREF
CK
CK
C1
C0
11
D2, D3, D5, D6,
R
COUNTER
(internal node)
CLK
2-BIT
D8 to D14
D
R
D
R
LPS0
CLK
CLK
CE
PARITY
CHECK
Rev. 02 — 26 March 2007
11
0
1
1.8 V DDR2-667 configurable registered buffer with parity
(internal node)
LPS1
D
R
CLK
CE
11
D2, D3, D5, D6,
D8 to D14
D
R
CLK
D
R
CLK
0
1
1
0
SSTUA32866
002aaa650
11
11
© NXP B.V. 2007. All rights reserved.
Q2A, Q3A,
Q5A, Q6A,
Q8A to Q14A
Q2B, Q3B,
Q5B, Q6B,
Q8B to Q14B
PPO
QERR
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