PCF8591T NXP Semiconductors, PCF8591T Datasheet - Page 9

• Manufacturer Part Number: PCF8591T
• Manufacturer: NXP Semiconductors
• Type: General Purposer

Specifications of PCF8591T

• Number Of Channels: 1
• Number Of Adc's: 1
• Number Of Dac's: 1
• Adc/dac Resolution: 8b
• Package Type: SO
• Interface Type: Serial (I2C)
• Operating Supply Voltage (typ): 3.3/5V
• Sample Rate: 11.1KSPS
• Number Of Adc Inputs: 4
• Number Of Dac Outputs: 1
• Operating Supply Voltage (max): 6V
• Operating Supply Voltage (min): 2.5V
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 16
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
7.4
The A/D converter makes use of the successive
approximation conversion technique. The on-chip D/A
converter and a high-gain comparator are used
temporarily during an A/D conversion cycle.
An A/D conversion cycle is always started after sending a
valid read mode address to a PCF8591 device. The A/D
conversion cycle is triggered at the trailing edge of the
acknowledge clock pulse and is executed while
transmitting the result of the previous conversion (see
Fig.9).
Once a conversion cycle is triggered an input voltage
sample of the selected channel is stored on the chip and is
2003 Jan 27
handbook, full pagewidth
8-bit A/D and D/A converter
PROTOCOL
A/D conversion
SDA
SCL
S
1
ADDRESS
2
1
8
A
9
conversion of byte 1
Fig.9 A/D conversion sequence.
sampling byte 1
1
converted byte
DATA BYTE 0
transmission
of previously
9
converted to the corresponding 8-bit binary code. Samples
picked up from differential inputs are converted to an 8-bit
twos complement code (see Figs 10 and 11).
The conversion result is stored in the ADC data register
and awaits transmission. If the auto-increment flag is set
the next channel is selected.
The first byte transmitted in a read cycle contains the
conversion result code of the previous read cycle. After a
Power-on reset condition the first byte read is a
hexadecimal 80. The protocol of an I
shown in Chapter 8, Figs 16 and 17.
The maximum A/D conversion rate is given by the actual
speed of the I
A
9
conversion of byte 2
1
sampling byte 2
DATA BYTE 1
transmission
of byte 1
2
C-bus.
A
9
1
conversion of byte 3
sampling byte 3
DATA BYTE 2
transmission
of byte 2
2
Product specification
C-bus read cycle is
PCF8591
A
MBL829