BBT3821-JH Intersil, BBT3821-JH Datasheet

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... Long Run Length (512 bit) Frequency Lock Ideal for Proprietary Encoding Schemes • Extensive Configuration and Status Reporting via 802.3 Clause 45 Compliant MDC/MDIO Serial Interface • Automatic Load of BBT3821 Control and all XENPAK Registers from EEPROM or DOM Circuit Figure 1. FUNCTIONAL BLOCK DIAGRAM Deserializer ...

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... Serial Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MDIO Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Space Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NVR Registers & EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auto-Configuring Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DOM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . General Purpose (GPIO) Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LASI Registers & I Reading Additional EEPROM Space Via the I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Writing EEPROM Space through the I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2 BBT3821 ...

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... AC and Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CX4/LX4/XAUI Re-timer Setup Recommended Analog Power and Ground Plane Splits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XENPAK/XPAK/X2 Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CX4 Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LX4 Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MDIO/MDC Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DOM Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LASI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Intersil Corporation Contact Information BBT3821 ...

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... Figure 19. I2C BUS INTERFACE PROTOCOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 20. NVR/DOM SEQUENTIAL READ OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 21. NVR SEQUENTIAL WRITE ONE PAGE OPERATION Figure 22. I2C SINGLE BYTE READ OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 23. SINGLE BYTE WRITE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 24. I2C OPERATION TIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 25. VDDPR CLAMP CIRCUIT Figure 26. RESISTIVE DIVIDER CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 BBT3821 ...

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... Table 39. PMA CONTROL 2 REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 40. PMA SERIAL LOOP BACK CONTROL REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 41. PMA PRE-EMPHASIS CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 42. PMA PRE-EMPHASIS CONTROL SETTINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 43. PMA/PMD EQUALIZATION CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 44. PMA SIG_DET AND LOS DETECTOR STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 45. PMA/PMD MISCELLANEOUS ADJUSTMENT REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 46. PMA/PMD/PCS/PHY XS SOFT RESET REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 BBT3821 ...

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... Table 86. PHY XS XAUI PRE-EMPHASIS CONTROL SETTINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 87. PHY XS EQUALIZATION CONTROL Table 88. PHY XS RECEIVE PATH TEST AND STATUS FLAGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 89. PHY XS OUTPUT AND TEST FUNCTION CONTROL REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 90. PHY XS STATUS 4 LOS DETECTOR REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 91. PHY XS CONTROL REGISTER Table 92. AUTO-CONFIGURE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 93. JTAG OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 94. CLOCK PINS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 BBT3821 ...

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... Table 114. RECEIVE SERIAL DIFFERENTIAL INPUT TIMING REQUIREMENTS (SEE Figure 11 Table 115. MDIO INTERFACE TIMING (FROM IEEE802.3AE) (SEE Figure 15 TO Figure 17 Table 116. RESET AND MDIO TIMING (SEE Figure 17 Table 117. RESET AND I2C SERIAL INTERFACE TIMING (SEE Figure 18 AND Figure 24 BBT3821 ...

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... Encoder, AKR Generator Ingress 8B/10B TXP2 P/N Encoder, AKR Generator 8B/10B TXP3 P/N Encoder, AKR Generator Device Address 4 PHY XGXS 8 BBT3821 JTAG MDIO Register, LASI & Common Logic RX FIFO Deskew 10B/8B Decoder RX FIFO Deskew 10B/8B Decoder RX FIFO Deskew 10B/8B Decoder RX FIFO ...

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... NVR and DOM support. The XPAK and X2 specifications currently all reference the XENPAK specification, and are supported in exactly the same manner. The BBT3821 can also be used to enhance a single full-duplex 10 Gigabit XAUI link, extending the driving distance of the high-speed (2.488Gbps to 3.1875Gbps) differential traces to 40 inches of FR4 PCB (assuming a proper impedance-controlled layout) ...

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... PCS_SYNC_EN bits, for the PCS at address 3.C000’h (Table 63), for the PHY XS at address 4.C000’h (Table 80), 10 BBT3821 unless overridden by the respective XAUI_EN bits in the [3,4].C001’h registers (Table 64 and Table 81 full code group may be deleted or modified while aligning the “ ...

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... IDLE-to- non-IDLE transition is detected again on the lanes. During this alignment four code groups may be deleted on any lane. For correct operation, the XAUI Lane 0 signals should be connected to the BBT3821 Lane 0 pins. The deskew algorithm state machines (each implemented according to IEEE 802.3ae) are enabled by setting the DSKW_SM_EN bits (Address [3,4].C000’ ...

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... Note (2): Default value, actually set by ‘Internal Idle’ register, [3:4].C003’h, see Table 67 and Table 83. Note (3): Value set by ‘ERROR Code’ register, [3:4].C002’h, see Table 66 and Table 66. The XAUI_EN bit forces it to 1FE’h. Note (4): If the XAUI_EN bit is set, the BBT3821 acts as though both the TRANS_EN and AKR_EN bits are set. 12 BBT3821 another column containing a non-idle is received ...

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... IEEE 802.3 rules). The BBT3821 will handle this according to those rules. In addition, the MDIO system includes a flag, in registers [3,4].C007’h on bits 11:8 (see Table 69 and Table 88). Similarly, an error in the PCS or PHY XS Elastic (clock compensation) FIFOs will be flagged in bits 7:4 of the same registers ...

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... IEEE 802.3ae-2002 specification for a 10GBASE-X PCS, the default is to NOT enable this loopback bit, and enabled, the BBT3821 does not conform to the IEEE specification. A maintenance request has been submitted to the IEEE to enable this loopback bit as optional, and to allow a ‘PCS Loopback Capability’ ...

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... Vendor Specific registers for each DEVAD respectively. The latter have been placed in the blocks beginning at D.C000’ avoid the areas currently defined as for use by the XENPAK module and similar MSA devices, to facilitate use of the BBT3821 in such modules and systems. Table 3. MDIO MANAGEMENT FRAME FORMATS PHYAD ...

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... I space, the BBT3821 will examine the Auto-configure Pointer value at 1.33029 (1.8105’h). If this is neither 00’h or FF’h, the BBT3821 will use that value (S below offset pointer into the A0.00:FF’h I MDIO NVR space, and the number of bytes given in the Auto-configure Size register 1 ...

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... LASI. The available inputs depend on the LX4/CX4 select LX4_MODE pin (Table 99), and are detailed in Table 27 and Table 28, and include: 1. Various status bits within the BBT3821, derived from its operations; in particular, the LOS indications, Byte Sync and EFIFO errors, the Fault bits [1,3,4].8.10:11, etc. ...

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OPTX OPT OPTX TX_ LBC TEMP LOP FAULT REG. REG. REG 4.C00Ah. REG 1.C01Dh.2:0 4.24.3:0 1.C012h.13 3:0 ALARM PIN POLARITY POLARITY PHY XS PHY XS LOS BYTE (SIG DET) SYNCH See IEEE Clear on read REGISTER 1.9004h.[10:0] TX_ALARM_STATUS REGISTER 1.9001h[10:0] ...

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... I C register space. Many DOM circuits protect their important internal data through some form of password protection, and in general the BBT3821 will allow this to be done without a problem. BLOCK WRITES TO EEPROM SPACE The first method is applicable only to the NVR space (I address space A0.00:FF’ ...

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... Note (5): For rows with “A”, the default value may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details). Note (6): IEEE 802.3 shows as R/W, but cannot write any other value than that set by LX4_MODE Pin. 20 BBT3821 PMA/PMD DEVICE 1 MDIO REGISTERS DESCRIPTION PMD Extended Capability PMD Package OUI, etc. NVR Control & ...

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... Speed Select 0000 = 10Gbps 1.0.1 Reserved 1.0.0 PMA Loopback 1 = Enable loopback 0 = Normal operation Note (1): After this RESET bit is written, the BBT3821 will not begin counting PREAMBLE bits immediately. See Figure 17 for details. BIT NAME 1.1.15:8 Reserved 1.1.7 Local Fault 1 = PMA Local Fault 1 ...

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... Extended Ability Register present. 1.8.8 TX Disable 1 = Can Disable TX 1.8.7 10GBASE- cannot perform 1.8.6 10GBASE- cannot perform 22 BBT3821 Table 8. IEEE DEVICES IN PACKAGE REGISTERS SETTING DEFAULT 000’h Link Partner PMA/PMD present 0’b 10PASS-TS tone table present 0’b DTE XS Present 0’b PHY XS Present 1’b PCS Present 1’ ...

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... Note (1): These bits reflect the OPRLOS[3:0] pins (Table 99) in LX4 mode, or the CX4 SIGNAL_DETECT function in CX4 mode, depending on the LX4_MODE select pin. Table 13. IEEE EXTENDED PMA/PMD CAPABILITY REGISTER BIT NAME 1.11.15:1 Reserved (1) 1.11.0 10GBASE-CX4 Note (1): These values reflect the IEEE 802.3ak 10GBASE-CX4 specification. 23 BBT3821 MDIO REGISTER ADDRESSES = 1.8 (1.0008’h) SETTING DEFAULT 0’b RO 1’b RO 0’b RO 0’b RO 0’ ...

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... Note (2): At the end of a hardware RESET via the RSTN pin, on powerup register [1,3,4].0.15 RESET operation, and if the XP_ENA pin is asserted, the BBT3821 will automatically begin an ‘all NVR read’ operation. Note (3): The single byte commands are controlled through the bits of the registers at 1.32769:32774 (1.8001:8006’h). The ‘block write/read’ commands are affected by register 1.32773 (1.8005’ ...

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... Note (2): These bits are set if the EXOR sum calculated from the indicated range is not the same as the value read into the listed checksum register. Note that this is NOT the same as the XENPAK-defined checksum calculation. Contact Intersil for a method of reconciling these two checksum calculations. 25 BBT3821 2 C ONE-BYTE OPERATION WRITE DATA REGISTER MDIO Register Address = 1.32772 (1.8004’ ...

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... Note (3): Although data can be written to this register, it should only be done for writing the NVR, using the ‘Write NVR’ operation as specified in “Writing EEPROM Space through the I2C Interface” on page 19. The values here should normally only be loaded from the NVR, since they could affect the operation of the BBT3821 if incorrect ...

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... Power up or RESET several LASI contributors will initially be in the ‘fault’ condition (in particular, Byte Synch and Lane Alignment, and their derivatives), it may be advisable for a host to clear these before enabling these to trigger LASI. Note (2): See description of the General Purpose Input/Output (GPIO) pins and bits for a description of how they contribute to the LASI system. 27 BBT3821 MDIO REGISTER, ADDRESS = 1.36864 (1.9000’h) (1) SETTING ...

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... Note (1): Where two descriptions are given, depends on LX4/CX4 select LX4_MODE pin. First value is LX4 value Note (2): These mirrored bits will be cleared on read of either this register or their respective registers. 28 BBT3821 Table 27. XENPAK LASI RX_ALARM STATUS REGISTER MDIO REGISTER, ADDRESS = 1.36867 (1.9003’h) ...

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... Note (1): These bits control (select) alarm signals (bits) in register 1.41073 (1.A071’h) to generate the RX_Flag bit of register 1.36867 (1.9003’h) to trigger RX_ALARM and hence LASI. Note (2): The default value may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details). 29 BBT3821 Table 29. XENPAK LASI STATUS REGISTER MDIO REGISTER, ADDRESS = 1.36869 (1.9005’h) SETTING DEFAULT 000’ ...

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... Note (1): These1-byte register values are merely copied by the BBT3821 from the I operation (i.e. with Register bit 1.C018’h.2 Table 51 not set) under the control of Register 1.A100’h (Table 38). For further details see Table 27 in the XENPAK MSA Rev 3.0 specification, especially Note desired to write this data into a DOM device through the MDIO interface, it will need to be written one byte at a time via the methods discussed in “ ...

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... Ready Note (1): This 1-byte register value is merely copied by the BBT3821 from the I update operation (i.e. with Register bit 1.C018’h.2 Table 51 not set) under the control of Register 1.A100’h (Table 38). The BBT3821 takes no action as a result of the values copied. Note (2): Assumes NVR/DOM read succeeds ...

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... Reserved Note (1): These 1-byte register values are merely copied by the BBT3821 from the I DOM update operation (i.e. with Register bit 1.C018’h.2 Table 51 not set) under the control of Register 1.A100’h (Table 38). The BBT3821 takes no action as a result of the values copied. ...

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... Reserved Note (1): These 1-byte register values are merely copied by the BBT3821 from the I DOM Enable’ bit (Register bit 1.C018’h.2 Table 51) is not set, a four-lane external DOM device is expected to determine the values for these registers, according Section 11.3 in the XENPAK MSA Rev 3.0 specification. A single one-lane DOM device system will provide the values from the single DOM device here. If the ‘ ...

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... Note (3): This is the Default value set on power-up or RESET if the LX4/CX4 LX4_MODE pin is set for CX4 operation. This setting allows for a small loss in the PCB traces and connectors before the IEEE 802.3akD5.3 defined TP2 compliance measurement point. The value may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details). 34 BBT3821 MDIO REGISTER ADDRESS = 1.49156 (1.C004’h) SETTING DEFAULT ...

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... Note (1): This reset will NOT cause a reload of the NVR or DOM areas, nor an Auto-Configure operation. It will reset the Byte Sync engine, the Lane Alignment engine, 2 the FIFO pointers, and the I C controller. The BBT3821 will (if “normally” configured) transmit ||LF|| local fault signals until Byte Sync and Lane Alignment are re-established, and any DOM update in progress may be aborted. 35 BBT3821 Table 43 ...

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... Reserved 1.49171.4:0 GPIO Pin Output Note (1): The value may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details). 36 BBT3821 Table 47. GPIO PIN DIRECTION CONFIGURE REGISTER MDIO REGISTER ADDRESS = 1.49168 (1.C010’h) SETTING DEFAULT ( output 00’ input Table 48 ...

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... Lane 0 DOM 1.49180.0 Not used, Set by current operation Note (1): The values may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details). 37 BBT3821 Table 51. DOM CONTROL REGISTER MDIO REGISTER ADDRESS = 1.49176 (1.C018’h) (1) SETTING DEFAULT 0’b See Table 52 00’ ...

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... Note (4): The IEEE 802.3ae specification allows this to be all zeroes. A XENPAK (etc.) host can more readily determine where the NVR registers are if this value is zero. Note (5): If IEEE 802.3ae (and default) setting for PCS Loopback, 180F’h. If PCS Loopback allowed, 1C0F’h. See Table 61 and Table 64. 38 BBT3821 MDIO REGISTER ADDRESS = 1.49181 (1.C01D’h) (1) ...

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... Many XENPAK hosts, however, expect this loopback (which is mandatory for 10GBASE-R PCS devices). Setting the 3.C001’h.7 bit, (Table 64) will activate this loopback enable bit, but cause the BBT3821 to be non-conforming to the current 802.3 specification. See “ ...

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... PCS TestPatEn Transmit Test Pattern Enable 3.25.1:0 PCS TestPat Test pattern Type select Note (1): For other test pattern generation capabilities incorporated in the BBT3821, including CJPAT and CRPAT, see Table 72. 40 BBT3821 MDIO REGISTER ADDRESS = 3.8 (3.0008’h) SETTING DEFAULT 10’b RO 0’ 0’ ...

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... If the incoming data is NOT frequency-synchronous with the local reference clock, data will be corrupted (occasional characters will be lost, or repeated). BIT NAME 3.49153.15:12 Reserved 3.49153.11 PCS XAUI_EN 3.49153.10:8 Reserved 3.49153.7 EN_PCSLB_EN 41 BBT3821 Table 63. PCS CONTROL REGISTER 2 MDIO REGISTER ADDRESS = 3.49152 (3.C000’h) (1) SETTING DEFAULT R/W 00’b 00’b R/W 1’b R disable 1’ ...

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... Note (2): PCS loopback via bit 3.0.14 (Table 57) is NOT permitted by IEEE 802.3ae-2002 for 10GBASE-X PCS devices. Many XENPAK hosts, however, expect this loopback (which is mandatory for 10GBASE-R PCS devices). Setting this bit will enable this loopback, but cause the BBT3821 to be non-conforming to the current 802.3 specification. See “ ...

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... ENA_2 Enable Lane 2 O/P 3.49160.8:6 Reserved 3.49160.5 ENA_1 Enable Lane 1 O/P 3.49160.12:10 Reserved 3.49160.1 ENA_0 Enable Lane 0 O/P 3.49160.0 Reserved 43 BBT3821 MDIO REGISTER ADDRESS = 3.49156 (3.C004’h) SETTING DEFAULT R/W (1) 0’b R/W (2) (1) 0’b (1) 0’b (1) 0’b MDIO REGISTER ADDRESS = 3.49159 (3.C007’h) ...

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... Note (3): This pattern is an /S/, preamble, the ‘Short PRBS23’ pattern, one /T/, and 9 /K/s, repeated. Note (4): A Soft Reset is required to activate the newly selected pattern. Note (5): The checker expects at least one /K/ on each lane between pattern repeats 44 BBT3821 SETTING DEFAULT 0’h 1’b = half rate clock 0’b = full 0’ ...

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... Note (3): Read value depends on status signal values. Value shown indicates ‘normal’ operation. Note (4): The IEEE 802.3ae spec allows this to be all zeroes. A XENPAK (etc.) host can more readily determine where the NVR registers are if this value is zero. 45 BBT3821 Table 73. BIST ERROR COUNTER REGISTERS MDIO REGISTER ADDRESSES = 3.49165:6 (3.C00D:E’h) ...

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... Note (1): These bits are latched high on any Fault condition detected. They are reset low (cleared) on being read. They will also be reset low on reading the LASI registers 1.9003’h (bit 10, see Table 27) or 1.9004’h (bit 11, see Table 28) 46 BBT3821 Table 75. IEEE PHY XS CONTROL 1 REGISTER MDIO REGISTER ADDRESS = 4.0 (4.0000’h) ...

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... PHY XS Receive Test Pattern TestPatEn Enable 4.25.1:0 PHY XS TestPat Test pattern select (see Type Table 72 for other test patterns generated by the BBT3821) VENDOR-SPECIFIC PHY XS REGISTERS (4.C000’H TO 4.C00B’H) BIT NAME 4.49152.15:14 Test Mode 4.49152.13:12 Reserved 4.49152.11 PHY XS Clock PSYNC 4 ...

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... PHY XS TRANS_EN 1 = enable 0 = disable Overridden by PHY XS XAUI_EN, see Table 65 4.49153.4 Reserved 4.49153.3 PHY XS TX_SDR PHY XS receive data rate 48 BBT3821 Table 80. PHY XS CONTROL REGISTER 2 (Continued) MDIO REGISTER ADDRESS = 4.49152 (4.C000’h) (1) SETTING DEFAULT R/W ( disable 0’b R enable 1 = enable 1’b ...

Page 49

... Note (1): Loopback is from XAUI Serial I/P to Serial O/P. Recommended use for test purposes only; no retiming or pre-emphasis is performed Note (2): These values may be overwritten by the Auto-Configure operation (See “Auto-Configuring Control Registers” on page 16 and Table 92 for details). 49 BBT3821 Table 81. PHY XS CONTROL REGISTER 3 (Continued) MDIO REGISTER ADDRESS = 4.49153 (4.C001’h) ...

Page 50

... Note (1): These bits are latched high on any Fault condition detected. They are reset low (cleared) on being read. They will also be reset low on reading the LASI register 1.9004’h (see Table 28) Note (2): See also error counters in registers 3.C00D:E’h (Table 73) 50 BBT3821 Table 85. PHY XS PRE-EMPHASIS CONTROL MDIO REGISTER ADDRESS = 4.49157 (4.C005’h) (1) ...

Page 51

... 4.49157.[15: 1.49158.[3: 1.49157.[7: 1.49157.[15: 1.36864.[6:0]. 51 BBT3821 MDIO REGISTER ADDRESS = 4.49160 (4.C008’h) SETTING DEFAULT 10’b Enable Lane 3 O/P 1’b 010’b Enable Lane 2 O/P 1’b 010’b Enable Lane 1 O/P 1’b 010’b Enable Lane 0 O/P 1’b 0’b Table 90. PHY XS STATUS 4 LOS DETECTOR REGISTER MDIO REGISTER ADDRESS = 4.49162 (4.C00A’ ...

Page 52

... Note (2): The target register pair are overlapped, ignoring the ‘reserved’ bits in one where used bits occur in the same location in the other. Thus the mapping from the NVR register is: 1.C001.[15:12], 3.C001.11, 1.C001.[10:8]. Note (3): The mapping from the NVR register is: 1.C004.[11:8], 3.C004.[3:0] 52 BBT3821 Table 92. AUTO-CONFIGURE REGISTERS (Continued) (1) HEX 1 ...

Page 53

... IPG allows for lane alignment (using the IDLE-to- NONIDLE transition alignment engine) and elasticity (by deleting or adding the requisite number of /K/s). The latter, in particular, allows one BBT3821 to check the ‘Short PRBS23’ or ‘Jumbo Ethernet Packet’ generated by another BBT3821 running on an independent clock within ±100 ppm. The full ...

Page 54

... BBT3821 The separate setup for BIST generation and checking means that two BBT3821s may be tested with a different pattern in each direction on the link between them. The signal flows provided for these BIST patterns are shown in Figure 6. The generator output may be injected (in place of the ‘ ...

Page 55

... Input (with pulldown) C8 TRSTN Input (with pullup) 55 BBT3821 Table 94. CLOCK PINS TYPE Differential Reference Input Clock. The reference input clock frequency is line rate clock frequency divided by 20 (full rate mode (half rate mode). The pins are internally biased at VDDA/2, and should be AC coupled. ...

Page 56

... B7 OPRLOS[0] D11 XP_ENA Input 56 BBT3821 Table 98. MANAGEMENT DATA INTERFACE PINS TYPE Management Address/Data I/O. 1.2V CMOS input, 2.5V Tolerant Management Interface Clock. 1.2V CMOS, 2.5V Tolerant, with Schmitt trigger Management Port Address Setting 1.2V CMOS Table 99. MISCELLANEOUS PINS Multi-function Outputs, Lanes The functions of these pins are enabled via the MDIO Interface ...

Page 57

... N16, P1, P2, P3, P16, R1, R8, R9, R14, R15, R16, T1, T2, T3, T6, T16 57 BBT3821 Table 99. MISCELLANEOUS PINS (Continued) Transmit enable input from XENPAK module input “TX ON/OFF”. Controls TX_ENA[3:0]. For normal operation, should be pulled active (default up). 1.2V CMOS Transmit Laser Driver Enables. They are set active only when TX_ENC pin is active and the corresponding bits in register 1 ...

Page 58

... VDDA 3 TCX0 GNDA TCX1 GNDA TCX0 GNDA TCX1 GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA GNDA BBT3821 FIGURE 7. TOP VIEW OF PINOUT GNDA RXP1 GNDA RXP0 GNDA TXP3 GNDA RXP1 GNDA RXP0 GNDA ...

Page 59

... Package Dimensions 59 BBT3821 FIGURE 8. EBGA-192 PACKAGE DIMENSIONS ...

Page 60

... Note (1): The ‘Max’ value is at the maximum supply voltages, while the ‘Typ’ value is at the nominal supply voltages. The power dissipation is not significantly affected by the V supply (see Table 111 for the distribution of power between the supplies). DDPR Note (2): The operating power varies slightly with the data pattern. The part is tested using a PRBS23 pattern. 60 BBT3821 Table 102. ABSOLUTE MAXIMUM RATINGS PARAMETER = 0°C to +85° ...

Page 61

... Note (1): Measured at TP3 as defined in the IEEE 802.3ak-2004 specifications. This value is needed in each IPG to maintain the SIG_DET function active. The -12 BBT3821 will provide a BER < Note (2): Measured at TP2 as defined in the IEEE 802.3ak-2004 specifications. Note (3): CX4 Mode not specified for low power Vdd = 1.35V operation; “Standard Device” conditions are required. ...

Page 62

... Note (1): The Maximum limit is measured using a PRBS23 pattern. The supply current for the CRPAT test pattern is very slightly lower, and for the CJPAT pattern is typically 20mA lower. Note (2): This Maximum limit refers to the LowPower part only, and is measured at 1.410V. 62 BBT3821 PARAMETER = 2 mA) OL ...

Page 63

... T Input Differential Skew DTOL (1,2) T Deterministic Jitter DJ T Total jitter tolerance JI -12 Note (1): Jitter specifications include all but 10 Note (2): Near end driven by BBT3821 Tx without pre-emphasis. 63 BBT3821 = 1.5V ± 5% (for the Standard Device DDAC DDAV DD DDA between V and 2.5V, unless otherwise specified. ...

Page 64

... Input Capacitance MD Note (1): The BBT3821 will accept a much higher MDC clock rate and shorter HI and LO times than the IEEE802.3 specification (section 22.2.2.11) requires. Such a faster clock may not be acceptable to other devices on the interface. Note (2): The BBT3821 MDIO registers will not be written until two MDC clocks have occurred after the frame end. These will normally count toward the minimum preamble before the next frame, except in the case of writing a RESET into [1,3,4] ...

Page 65

... Timing Diagrams TCX[3:0]P-N, TXP[3:0]P-N TCX[3:0]P, TXP[3:0]P TCX[3:0]N, TXP[3:0]N TXP[3:0]P/N, TCX[3:0]P/N TXP[3:0]P/N, TCX[3:0]P/N Vcm 65 BBT3821 FIGURE 9. DIFFERENTIAL OUTPUT SIGNAL TIMING DTOL FIGURE 10. LANE TO LANE DIFFERENTIAL SKEW T ODS FIGURE 11. EYE DIAGRAM DEFINITION Unit Interval (UI) Eye Width Vpp (single-ended) Total Jitter ...

Page 66

... Idle ----to---- Serialized RCX2 Idle Serialized RCX3 Idle Serialized TXP0 Idle ----to---- Idle Serialized TXP3 FIGURE 14. RETRANSMIT LATENCY Idle Data RCX[3:0]P-N, RXP[3:0]P-N TXP[3:0]P-N, TCX[3:0]P-N 66 BBT3821 Not Comma Comma Idle RT RT SYNC Error Random Comma RefCLK RXCLK Align Data Data Data RT Align SKEWIN Idle ...

Page 67

... MDIO (from STA) MDC MDIO (from MMD) T Register Contents FIGURE 16. MDIO INTERFACE TIMING STA MDIO MDD Sourced T MDC MDC MDIO STA Sourced T MDH 67 BBT3821 ST OP Prt/Dev Ad TA Address/Data T Preamble Old Data MMD TA (for READ Ops) T MDSU Idle/Preamble Update New Data MMD STA ...

Page 68

... RESET RSTN SCL SDA T WAIT Control Registers FIGURE 19. I SDA MSB S SCL START or repeated START condition 68 BBT3821 (Internal States, not observable) T MDRST 1 st preamble bit 2 C NVR READ AT THE END OF RESET train wait Read NVR Read DOM T TRAIN T WAIT Default Data ...

Page 69

... write data write data FIGURE 22 SINGLE BYTE READ OPERATION word addr slave addr FIGURE 23. SINGLE BYTE WRITE OPERATION slave addr W word addr W 69 BBT3821 read data slave addr A no ACK C K last read data write data write data A no ACK C K ...

Page 70

... SCL SDA Applications Information CX4/LX4/XAUI Re-timer Setup This section discusses the setup for the BBT3821 to be used as a XAUI/CX4/LX4 Retimer. The various descriptions and comments further assume that the device is initially configured in the default condition (i.e. exactly as found after a hardware reset). The BIST_ENA pin should be pulled LOW (to GND) ...

Page 71

... The BBT3821 incorporates a number of features that facilitate interface to the (pin-function-compatible) XENPAK, XPAK and X2 interfaces. The relevant 3.125Gbps serial lines in the BBT3821-JH are brought out in exactly the correct order to be connected to the edge connector, minimizing any layout problems, and the use of vias, in PCB design. ...

Page 72

... CX4 Interfacing The relevant 3.125Gbps serial lines in the BBT3821-JH are brought out in exactly the correct order to be connected to the CX4 connector, using either the top layer of the PCB for striplines inner layer for microstrip lines, without any necessity for crossing the various leads. There are GNDA ...

Page 73

... A similar series of parts are available from Cyex as the SLC series. These parts also include DACs for Laser control functions. If this type of device is used, the BBT3821 should be set up in ‘Direct DOM’ mode (see Table 51 and "DOM Registers"), and it will then be able to download the complete DOM block as required ...

Page 74

... MIC3000 74 BBT3821 R2 10K R3 12K FIGURE 26. RESISTIVE DIVIDER CIRCUITS TX_FAULT TX_FAULT_3P3 - - - etc etc OPRXOP OPRXOP_3P3 TX_ENA3P3_# SDA, SCL FIGURE 25. V CLAMP CIRCUIT DDPR P3V3 From MSA Conn To BBT3821, Pull-Up Resistors Cathode Cathode 3 Reference Anode Anode ZHCS400 A LMV431 2 Rpu TX_FAULT_3P3 12K - - - etc Rpu ...

Page 75

... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 75 BBT3821 ORDER PART NUMBER BBT3821-JH BBT3821LP-JH ...