PCK9446BD,151 NXP Semiconductors, PCK9446BD,151 Datasheet - Page 9

• Manufacturer Part Number: PCK9446BD,151
• Description: IC FANOUT BUFFER LVCMOS 32LQFP
• Manufacturer: NXP Semiconductors
• Type: Fanout Buffer (Distribution), Divider, Multiplexerr

Specifications of PCK9446BD,151

• Number Of Circuits: 1
• Ratio - Input:output: 2:10
• Differential - Input:output: No/No
• Input: LVCMOS
• Output: LVCMOS
• Frequency - Max: 250MHz
• Voltage - Supply: 2.375 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 250MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3643-5; 935280839151; PCK9446BD-S

Philips Semiconductors
11. Application information
PCK9446_1
Product data sheet
11.1 Driving transmission lines
The PCK9446 clock driver was designed to drive high speed signals in a terminated
transmission line environment. To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance possible. With an output
impedance of less than 20
transmission lines.
In most high performance clock networks point-to-point distribution of signals is the
method of choice. In a point-to-point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel technique terminates the signal at
the end of the line with a 50
level of DC current and thus only a single terminated line can be driven by each output of
the PCK9446 clock driver. For the series terminated case however there is no DC current
draw, thus the outputs can drive multiple series terminated lines.
output driving a single series terminated line versus two series terminated lines in parallel.
When taken to its extreme, the fan-out of the PCK9446 clock driver is effectively doubled
due to its capability to drive multiple lines.
Fig 3. Single versus dual transmission lines
IN
IN
Rev. 01 — 10 April 2006
PCK9446
PCK9446
OUTPUT
BUFFER
OUTPUT
BUFFER
the drivers can drive either parallel or series terminated
resistance to 0.5V
14
14
R o
R o
R s = 36
R s = 36
R s = 36
2.5 V and 3.3 V LVCMOS clock fan-out buffer
CC
Z o = 50
Z o = 50
Z o = 50
. This technique draws a fairly high
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
002aaa708
OutA
OutB0
OutB1
Figure
PCK9446
3, illustrates an
9 of 17