MK2049-34SAI IDT, Integrated Device Technology Inc, MK2049-34SAI Datasheet - Page 4

• Manufacturer Part Number: MK2049-34SAI
• Description: IC VCXO PLL CLK SYNTH 20-SOIC
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Synthesizerr

Specifications of MK2049-34SAI

• Pll: Yes
• Input: Clock
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:3
• Differential - Input:output: No/No
• Frequency - Max: 77.76MHz
• Divider/multiplier: Yes/Yes
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC
• Frequency-max: 44.736MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Buffer Mode
Unlike the other two modes that accept only a single specified input frequency, Buffer Mode will accept a wider range of
input clocks. The input jitter is attenuated and the outputs on CLK and CLK/2 also provide the option of getting x1, x2, x4, or
1/2 of the input frequency. For example, this mode can be used to remove the jitter from a 27 MHz clock, generating
low-jitter 27 MHz and 13.5 MHz outputs.
Input and Output Synchronization
As shown in the tables on page 3, the MK2049-34A offers a Zero Delay feature in all selections. There is an internal
feedback path between ICLK and the output clocks, providing a fixed phase relationship between the input and output, a
requirement in many communication systems.
The rising edge of ICLK will be aligned with the rising edges of CLK and CLK/2 (8 kHz is used in this illustration, but the
same is true for the selections in the Loop Timing and Buffer Modes).
Measuring Zero Delay on the MK2049
The MK2049-34 produces low-jitter output clocks. In addition, this part has a very low bandwidth on the order of a few Hertz.
Since most 8 kHz input clocks will have high jitter, this can make measuring the input-to-output skew (zero delay feature)
very difficult. The MK2049 is designed to reject the input jitter; when the input and output clocks are both displayed on an
oscilloscope, they may appear not to be locked because the scope trigger point is constantly changing with the input jitter.
In fact, the input and output clocks probably are locked and the MK2049 will have zero delay to the average position of the
8 kHz input clock. In order to see this clearly, a low jitter 8 kHz input clock is necessary. Most lab frequency sources are NOT
SUITABLE for this since they have high jitter at low frequencies.
Frequency Locking to the Input
In all modes, the output clocks are frequency-locked to the input. The outputs will remain at the specified output frequency
as long as the combined variation of the input frequency and the crystal does not exceed 100 ppm. For example, if the
crystal can vary ±40 ppm (initial accuracy + temperature + aging), then the input frequency can vary by up to 60 ppm and
still have the output clock remain frequency-locked.
IDT™ / 3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL
MK2049-34A
3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL
F ig u r e 1 . M K 2 0 4 9 -3 4 In p u t a n d O u tp u t C lo c k W a v e fo r m s
C L K /2 (M H z )
IC L K (8 k H z )
C L K (M H z )
4
VCXO AND SYNTHESIZER
MK2049-34A REV E 051310