HCF4046BEY STMicroelectronics, HCF4046BEY Datasheet - Page 2

• Manufacturer Part Number: HCF4046BEY
• Description: IC PHASE-LOCK LOOP MCRPWR 16-DIP
• Manufacturer: STMicroelectronics
• Type: Phase Lock Loop (PLL)r

Specifications of HCF4046BEY

• Pll: Yes
• Input: CMOS
• Output: CMOS
• Number Of Circuits: 1
• Ratio - Input:output: 2:1
• Differential - Input:output: No/No
• Frequency - Max: 1.4MHz
• Divider/multiplier: No/No
• Voltage - Supply: 3 V ~ 20 V
• Operating Temperature: -55°C ~ 125°C
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• Frequency-max: 1.4MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

HCF4046B
VCO Section
The VCO requires one external capacitor C1 and
one or two external resistors (R1 or R1 and R2).
Resistor R1 and capacitor C1 determine the
frequency range of the VCO and resistor R2
enables the VCO to have a frequency offset if
required. The high input impedance (10
VCO simplifiers the design of low-pass filters by
permitting the designer a wide choice of
resistor-to-capacitor ratios. In order not to load the
low-pass filter, a source-follower output of the
VCO input voltage is provided at terminal 10
(DEMODULATED OUTPUT). If this terminal is
used, a load resistor (R
be connected from this terminal to V
this terminal should be left open. The VCO can be
connected either directly or through frequency
dividers to the comparator input of the phase
comparators. A full CMOS logic swing is available
at the output of the VCO and allows direct
coupling to CMOS frequency dividers such as the
HCF4024B, HCF4018B, HCF4020B, HCF4022B,
HCF4029B and HBF4059A.
HCF4018B (Presettable Divide-by-N Counter) or
HCF4029B (Presettable Up/Down Counter), or
HBF4059A
Counter),
(Phase-Locked Loop) can be used to build a
micropower low-frequency synthesizer. A logic 0
on the INHIBIT input "enables" the VCO and the
source follower, while a logic 1 "turns off" both to
minimize stand-by power consumption.
Phase Comparators
The phase-comparator signal input (terminal 14)
can be direct-coupled provided the signal swing is
within CMOS logic levels [logic "0"
(V
smaller swings the signal must be capacitively
coupled to the self-biasing amplifier at the signal
input. Phase comparator I is an exclusive-OR
network; it operates analagously to an over-driven
balanced mixer. To maximize the lock range, the
signal-and comparator-input frequencies must
have a 50% duty cycle. With no signal or noise on
the signal input, this phase comparator has an
average output voltage equal to V
low-pass filter connected to the output of phase
comparator I supplies the averaged voltage to the
VCO input, and causes the VCO to oscillate at the
center frequency (fo). The frequency range of
2/12
DD
-V
SS
), logic "1"
together
(Programmable
S
) of 10 K or more should
with
70% of (V
the
One
DD
Divide-by-"N"
SS
HCF4046B
-V
. If unused
DD
12
or
SS
/2. The
30% of
) of the
)]. For
more
input signals on which the PLL will lock if it was
initially out of lock is defined as the frequency
capture range (2 f
signals on which the loop will stay locked if it was
initially in lock is defined as the frequency lock
range (2 f
With phase comparator I the range of frequencies
over which the PLL can acquire lock (capture
range) is dependent on the low-pass-filter
characteristics, and can be made as large as the
lock range. Phase-comparator I enables a PLL
system to remain in lock in spite of high amounts
of noise in the input signal. One characteristic of
this type of phase comparator is that it may lock
onto input frequencies that are close to harmonics
of
characteristic is that the phase angle between the
signal and the comparator input varies between 0°
and 180°, and is 90° at the center frequency. Fig.1
shows the typical, triangular, phase-to-output
response characteristic of phase-comparator I.
Typical
phase-locked-loop employing phase comparator I
in locked condition of fo is shown in fig.2.
Phase-comparator II is an edge-controlled digital
memory network. It consists of four flip-flop
stages,
output-circuit comprising p- and n-type drivers
having a common output node. When the p-MOS
or n-MOS drivers are ON they pull the output up to
V
phase comparator acts only on the positive edges
of the signal and comparator inputs. The duty
cycles of the signal and comparator inputs are not
important since positive transitions control the PLL
system utilizing this type of comparator. If the
signal-input
comparator-input frequency, the p-type output
driver is maintained ON most of the time, and both
the n- and p-drivers OFF (3 state) the remainder of
the time. If the signal-input frequency is lower than
the comparator-input frequency, the n-type output
driver is maintained ON most of the time, and both
the n- and p-drivers OFF (3 state) the remainder of
the time. If the signal and comparator-input
frequencies are the same, but the signal input lags
the comparator input in phase, the n-type output
driver is maintained ON for a time corresponding
to the phase difference. If the signal and
comparator-input frequencies are the same, but
the comparator input lags the signal in phase, the
DD
the
or down to V
L
control
). The capture range is the lock range.
VCO
waveforms
frequency
C
center-frequency.
). The frequency range of input
gating,
SS
, respectively. This type of
is
and
for
higher
a
a
A
three-stage
than
second
CMOS
the