LTC6992HS6-1#TRMPBF Linear Technology, LTC6992HS6-1#TRMPBF Datasheet - Page 18

• Manufacturer Part Number: LTC6992HS6-1#TRMPBF
• Description: IC TIMERBLOX VOLT PWM TSOT23-6
• Manufacturer: Linear Technology

Specifications of LTC6992HS6-1#TRMPBF

• Frequency: *
• Voltage - Supply: *
• Current - Supply: 365µA
• Operating Temperature: *
• Package / Case: TSOT-23-6, TSOT-6
• Count: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LTC6992HS6-1#TRMPBFTR

OPERATION
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
Changing DIVCODE After Start-Up
Following start-up, the A/D converter will continue
monitoring V
be recognized slowly, as the LTC6992 places a priority on
eliminating any “wandering” in the DIVCODE. The typical
delay depends on the difference between the old and
new DIVCODE settings and is proportional to the master
oscillator period.
A change in DIVCODE will not be recognized until it is
stable, and will not pass through intermediate codes.
A digital filter is used to guarantee the DIVCODE has settled
to a new value before making changes to the output. Then
the output will make a clean (glitchless) transition to the
new divider setting.
18
t
DIVCODE
0.5V/DIV
1V/DIV
OUT
DIV
Figure 5. DIVCODE Change from 3 to 1
= 16 • (ΔDIVCODE + 6) • t
V
R
V
DIV
+
SET
MOD
= 3.3V
= 200k
for changes. Changes to DIVCODE will
= 0.3V
100μs/DIV
512μs
MASTER
6992 F05
Start-Up Time
When power is first applied, the power-on reset (POR)
circuit will initiate the start-up time, t
is held low during this time. The typical value for t
ranges from 0.5ms to 8ms depending on the master oscil-
lator frequency (independent of N
The output will begin oscillating after t
the first pulse has the correct width. If POL = 1 (DIVCODE
≥ 8), the first pulse width can be shorter or longer than
expected, depending on the duty cycle setting, and will
never be less than 25% of t
During start-up, the DIV pin A/D converter must determine
the correct DIVCODE before the output is enabled. The
start-up time may increase if the supply or DIV pin volt-
ages are not stable. For this reason, it is recommended to
minimize the capacitance on the DIV pin so it will properly
track V
t
OUT
DIV
START(TYP)
V
+
+
. Less than 100pF will not affect performance.
Figure 6. Start-Up Timing Diagram
= 500 • t
1ST PULSE WIDTH MAY BE INACCURATE
t
START
MASTER
t
STABLE V
DIVCODE
OUT
DIV
.
DIV
):
START
START
. The OUT pin
. If POL = 0
6992 F06
69921234f
START