LTC6992HS6-1#TRMPBF Linear Technology, LTC6992HS6-1#TRMPBF Datasheet - Page 22

• Manufacturer Part Number: LTC6992HS6-1#TRMPBF
• Description: IC TIMERBLOX VOLT PWM TSOT23-6
• Manufacturer: Linear Technology

Specifications of LTC6992HS6-1#TRMPBF

• Frequency: *
• Voltage - Supply: *
• Current - Supply: 365µA
• Operating Temperature: *
• Package / Case: TSOT-23-6, TSOT-6
• Count: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LTC6992HS6-1#TRMPBFTR

APPLICATIONS INFORMATION
LTC6992-1/LTC6992-2/
LTC6992-3/LTC6992-4
Power Supply Current
The power supply current varies with frequency, supply
voltage and output loading. It can be estimated under any
condition using the following equation:
SUPPLY BYPASSING AND PCB LAYOUT GUIDELINES
The LTC6992 is a 2.4% accurate silicon oscillator when
used in the appropriate manner. The part is simple to use
and by following a few rules, the expected performance
is easily achieved. Adequate supply bypassing and proper
PCB layout are important to ensure this.
Figure 14 shows example PCB layouts for both the TSOT-23
and DFN packages using 0603 sized passive components.
The layouts assume a two layer board with a ground plane
layer beneath and around the LTC6992. These layouts are
a guide and need not be followed exactly.
If N
If N
22
L+
L+ V
L+
I
I
S(TYP)
S(TYP)
DIV
DIV
320kΩ
320kΩ
= 1 (DIVCODE = 0 or 15):
> 1 (DIVCODE = 1 or 14):
+
V
V
≈ V
≈ V
• f
+
+
OUT
+
+
• N
+
+
• f
OUT
V
• 28pF + C
V
DIV
(
+
+
• Duty Cycle
• Duty Cycle
• 39pF + C
• f
R
R
(
LOAD
LOAD
OUT
• 27pF
LOAD
LOAD
)
+ 2.2 •I
+ 2.6 •I
)
SET
SET
+ 85µA
+ 90µA
1. Connect the bypass capacitor, C1, directly to the V
2. Place all passive components on the top side of the
3. Place R
4. Connect R
5. Use a ground trace to shield the SET pin. This provides
6. Place R1 and R2 close to the DIV pin. A direct, short
GND pins using a low inductance path. The connection
from C1 to the V
layer. For the DFN package, C1’s connection to GND is
also simply done on the top layer. For the TSOT-23, OUT
can be routed through the C1 pads to allow a good C1
GND connection. If the PCB design rules do not allow
that, C1’s GND connection can be accomplished through
multiple vias to the ground plane. Multiple vias for both
the GND pin connection to the ground plane and the
C1 connection to the ground plane are recommended
to minimize the inductance. Capacitor C1 should be a
0.1μF ceramic capacitor.
board. This minimizes trace inductance.
make a direct, short connection. The SET pin is a
current summing node and currents injected into this
pin directly modulate the operating frequency. Having
a short connection minimizes the exposure to signal
pickup.
or vias to the ground plane will not have a significant
affect on accuracy, but a direct, short connection is
recommended and easy to apply.
another layer of protection from radiated signals.
connection to the DIV pin minimizes the external signal
coupling.
SET
SET
as close as possible to the SET pin and
directly to the GND pin. Using a long path
+
pin is easily done directly on the top
69921234f
+
and