M41T81SM6F STMicroelectronics, M41T81SM6F Datasheet - Page 9

• Manufacturer Part Number: M41T81SM6F
• Description: IC RTC SERIAL W/ALARM 8SOIC
• Manufacturer: STMicroelectronics
• Type: Clock/Calendar/Alarmr

Specifications of M41T81SM6F

• Memory Size: 20B
• Time Format: HH:MM:SS:hh (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Function: Clock/Calendar/Alarm/Timer Interrupt
• Rtc Memory Size: 20 Byte
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Rtc Bus Interface: Serial (I2C)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-4684-2

M41T81S
2
2-wire bus characteristics
Operation
The M41T81S clock operates as a slave device on the serial bus. Access is obtained by
implementing a start condition followed by the correct slave address (D0h). The 20 bytes
contained in the device can then be accessed sequentially in the following order:
1. Tenths/hundredths of a second register
2. Seconds register
3. Minutes register
4. Century/hours register
5. Day register
6. Date register
7. Month register
8. Year register
9. Calibration register
10. Watchdog register
11 - 15. Alarm registers
16. Flags register
17 - 19. Reserved
20. Square wave register
The M41T81S clock continually monitors V
fall below V
counter. Inputs to the device will not be recognized at this time to prevent erroneous data
from being written to the device from a an out-of-tolerance system. Once V
switchover voltage (V
down into an ultra-low current mode of operation to preserve battery life. If V
V
greater than V
V
above V
For more information on battery storage life refer to application note AN1012.
The bus is intended for communication between different ICs. It consists of two lines: a bi-
directional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be
connected to a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
●
●
●
PFD
PFD
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is high.
Changes in the data line, while the clock line is high, will be interpreted as control
signals.
, the device power is switched from V
. Upon power-up, the device switches from battery to V
PFD
PFD
, it will recognize the inputs.
PFD
, the device terminates an access in progress and resets the device address
, the device power is switched from V
SO
), the device automatically switches over to the battery and powers
Doc ID 10773 Rev 6
CC
CC
to V
for an out-of-tolerance condition. Should V
BAT
when V
CC
to V
CC
CC
BAT
at V
drops below V
when V
SO
. When V
CC
CC
BAT
falls below the
drops below
BAT
CC
is less than
Operation
. If V
rises
BAT
9/32
CC
is