ISL12028IV27Z-T Intersil, ISL12028IV27Z-T Datasheet - Page 29

IC RTC EEPROM LP 14-TSSOP

ISL12028IV27Z-T

Manufacturer Part Number
ISL12028IV27Z-T
Description
IC RTC EEPROM LP 14-TSSOP
Manufacturer
Intersil
Type
Clock/Calendar/Supervisor/EEPROMr
Datasheet

Specifications of ISL12028IV27Z-T

Memory Size
4K (512 x 8)
Time Format
HH:MM:SS (12/24 hr)
Date Format
YY-MM-DD-dd
Interface
I²C, 2-Wire Serial
Voltage - Supply
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
14-TSSOP
Rohs Compliant
YES
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ISL12028IV27Z-TTR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISL12028IV27Z-T
Manufacturer:
Intersil
Quantity:
2 500
Part Number:
ISL12028IV27Z-T
Manufacturer:
Intersil
Quantity:
39 253
Package Outline Drawing
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 3, 10/09
6.40
0.20 C B A
4.40 ±0.10
2
SEATING
PLANE
C
(0.65 TYP)
(5.65)
0.10 C
TYPICAL RECOMMENDED LAND PATTERN
3
H
14
1
29
5.00 ±0.10
SIDE VIEW
TOP VIEW
0.65
1
0.25 +0.05/-0.06
0.10
3
0.05
8
7
CBA
A
I.D. MARK
(0.35 TYP)
PIN #1
ISL12028, ISL12028A
1.20 MAX
(1.45)
B
5
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
2. Dimension does not include interlead flash or protrusion. Interlead
3. Dimensions are measured at datum plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
6. Dimension in ( ) are for reference only.
7. Conforms to JEDEC MO-153, variation AB-1.
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
flash or protrusion shall not exceed 0.25 per side.
shall be 0.80mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead is 0.07mm.
0.90 +0.15/-0.10
0.15 MAX
0.05 MIN
DETAIL "X"
SEE
0.09-0.20
DETAIL "X"
END VIEW
1.00 REF
GAUGE
PLANE
0.60 ±0.15
0°-8°
November 30, 2010
0.25
FN8233.9

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