M41T56M6F STMicroelectronics, M41T56M6F Datasheet - Page 10

• Manufacturer Part Number: M41T56M6F
• Description: IC RTC SRL 512BIT 8SOIC
• Manufacturer: STMicroelectronics
• Type: Clock/Calendar/NVSRAMr

Specifications of M41T56M6F

• Memory Size: 56B
• Time Format: HH:MM:SS (24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Function: Clock, Calendar
• Rtc Memory Size: 64 B
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Rtc Bus Interface: Serial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-4706-2

2.2
10/25
Table 2.
1. Valid for ambient operating temperature: T
2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max.) of the falling
Read mode
In this mode, the master reads the M41T56 slave after setting the slave address (see
Figure 7 on page 11
= 0) and the Acknowledge Bit, the word address A
Next the START condition and slave address are repeated, followed by the READ Mode
Control Bit (R/W = 1). At this point, the master transmitter becomes the master receiver. The
data byte which was addressed will be transmitted and the master receiver will send an
Acknowledge Bit to the slave transmitter. The address pointer is only incremented on
reception of an Acknowledge Bit. The M41T56 slave transmitter will now place the data byte
at address A
and the address pointer is incremented to A
addresses will continue until the master receiver sends a STOP condition to the slave
transmitter.
An alternate READ mode may also be implemented, whereby the master reads the M41T56
slave without first writing to the (volatile) address pointer. The first address that is read is the
last one stored in the pointer, see
t
Symbol
HD:DAT
t
t
t
t
edge of SCL.
SU:STO
HD:STA
SU:STA
SU:DAT
t
t
f
t
HIGH
LOW
SCL
BUF
t
t
R
F
(2)
n
AC characteristics
SCL clock frequency
Clock low period
Clock high period
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
(after this period the first clock pulse is generated)
START condition setup time
(only relevant for a repeated start condition)
Data setup time
Data hold time
STOP condition setup time
Time the bus must be free before a new
transmission can start
+ 1 on the bus. The master receiver reads and acknowledges the new byte
and
Figure 8 on page
Parameter
Figure 9 on page
A
= –40 to 85°C; V
(1)
11). Following the WRITE Mode Control Bit (R/W
n
+ 2. This cycle of reading consecutive
n
is written to the on-chip address pointer.
11.
CC
= 4.5 to 5.5V (except where noted).
Min
250
4.7
4.7
4.7
4.7
0
4
4
0
Max
100
300
1
Unit
kHz
µs
µs
µs
ns
µs
µs
ns
µs
µs
µs