ISL12025IBZ Intersil, ISL12025IBZ Datasheet
ISL12025IBZ
Specifications of ISL12025IBZ
Related parts for ISL12025IBZ
ISL12025IBZ Summary of contents
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... PART V RANGE RESET (Note) MARKING VOLTAGE (°C) ISL12025IBZ* 12025 IBZ 2.63V - SOIC ISL12025IVZ* 2025 IVZ 2.63V - TSSOP M8.173 *Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special ...
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Block Diagram X1 32.768KHZ X2 CONTROL SCL SERIAL DECODE INTERFACE LOGIC DECODER SDA 8 RESET Pin Descriptions PIN NUMBER SOIC TSSOP SYMBOL The X1 pin is the input of an inverting amplifier and is intended to be ...
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... Output Low Voltage OL I Output Leakage Current LO 3 ISL12025 Thermal Information Thermal Resistance (Typical, Note SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . 8 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp = +2.7V to +5.5V 3.3V. DD CONDITIONS CONDITIONS (Note 12 2. 5.5V ...
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Watchdog Timer/Low Voltage Reset Parameters SYMBOL PARAMETER t V Detect to RESET LOW RPD DD t Power-up Reset Time-Out Delay PURST V Minimum V for Valid RESET RVALID DD Output V ISL12025-4.5A Reset Voltage RESET Level ISL12025 Reset Voltage Level ...
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Serial Interface (I C) Specifications SYMBOL PARAMETER t Clock LOW Time LOW t Clock HIGH Time HIGH t START Condition Set-up Time SU:STA t START Condition Hold Time HD:STA t Input Data Set-up Time SU:DAT t Input Data Hold ...
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Timing Diagrams SCL t SU:STA t HD:STA SDA (INPUT TIMING) SDA (OUTPUT TIMING) SCL SDA 8TH BIT OF LAST BYTE t RSP SCL SDA RESET START NOTE: ALL INPUTS ARE IGNORED DURING THE ACTIVE RESET PERIOD (t V RESET V ...
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Typical Performance Curves 4.0 BSW = 3.5 SCL, SDA PULL-UPS = 0V 3.0 2.5 2.0 1.5 SCL, SDA PULL-UPS = V 1.0 0.5 BSW = 0.0 1.8 2.3 2.8 3.3 3.8 V (V) BAT ...
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Description The ISL12025 device is a Real-Time Clock with clock/calendar, two polled alarms with integrated 512x8 EEPROM configured in 16 Bytes per page format, oscillator compensation, CPU Supervisor (Power-on Reset, Low Voltage Sensing and Watchdog Timer) and battery backup switch. ...
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... For example, a >20ppm frequency deviation translates into an accuracy of >1 minute per month. These parameters are available from the crystal manufacturer. Intersil’s RTC family provides on-chip crystal compensation networks to adjust load-capacitance to tune oscillator frequency from -34ppm to +80ppm when using a 12.5pF load crystal. For more detailed information see the “ ...
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DW: Day of the Week Register This register provides a Day of the Week status and uses three bits DY2 to DY0 to represent the seven days of the week. The counter advances in the cycle 0-1-2-3-4-5-6-0-1-2-… The assignment of ...
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REG ADDR. TYPE NAME 7 003F Status SR BAT 0037 RTC Y2K 0 (SRAM) 0036 DW 0 0035 YR Y23 0034 MO 0 0033 DT 0 0032 HR MIL 0031 MN 0 0030 SC 0 0027 ID7 ID77 0026 ID6 ...
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Alarm Registers (Non-Volatile) Alarm0 and Alarm1 The alarm register bytes are set up identical to the RTC register bytes, except that the MSB of each byte functions as an enable bit (enable = “1”). These enable bits specify which alarm ...
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A range from -30ppm to +30ppm can be represented by using the three ETR bits previously explained. TABLE 4. DIGITAL TRIMMING REGISTERS DTR REGISTER ESTIMATED FREQUENCY DTR2 DTR1 DTR0 ...
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... Many types of batteries can be used with Intersil RTC products. For example, 3.0V or 3.6V Lithium batteries are appropriate, and battery sizes are available that can power an Intersil RTC device for years. Another option is to use a Super Cap for applications where V for month. See the “Application Section” on page 21 for more information ...
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Standard Mode Power Switchover • Normal Operating Mode ( Battery Backup Mode BAT To transition from the BAT following conditions must be met: - Condition 1: V < ...
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TABLE 6. WD1 WD0 Watchdog Timer Restart The Watchdog Timer is started by a falling edge of SDA when the SCL line is high (START condition). The start signal restarts the Watchdog ...
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SCL SDA SCL FROM MASTER DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START FIGURE 18. ACKNOWLEDGE RESPONSE FROM RECEIVER DEVICE IDENTIFIER ARRAY CCR FIGURE 19. SLAVE ADDRESS, WORD ADDRESS, ...
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A zero selects a write operation. (see Figure 19). After loading the entire Slave Address Byte from the SDA bus, the ISL12025 compares the device identifier and device select bits with ‘1010111’ or ‘1101111’. Upon a correct ...
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SIGNALS FROM THE MASTER SDA BUS SIGNALS FROM THE SLAVE 6 BYTES ADDRESS = 5 ADDRESS POINTER ENDS AT ADDR = 5 FIGURE 21. WRITING 12 BYTES TO A 16-BYTE MEMORY PAGE STARTING AT ADDRESS SIGNALS FROM ...
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S T SIGNALS FROM SLAVE A THE MASTER R ADDRESS T SDA BUS SIGNALS FROM C THE SLAVE K FIGURE 23. CURRENT ADDRESS READ SEQUENCE BYTE LOAD COMPLETED BY ISSUING STOP. ENTER ACK POLLING ...
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... In addition to the analog compensation afforded by the adjustable load capacitance, a digital compensation feature is available for the Intersil RTC family. There are 3-bits known as the Digital Trimming Register or DTR, and they operate by adding or skipping pulses in the clock signal. The range provided is ± ...
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... Applying a scope probe can possibly cause a faulty oscillator to start-up, hiding other issues (although in the Intersil RTC’s, the internal circuitry assures startup when using the proper crystal and layout). ...
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... Backup Battery Operation Many types of batteries can be used with the Intersil RTC products. 3.0V or 3.6V Lithium batteries are appropriate, and sizes are available that can power a Intersil RTC device for years. Another option is to use a Super Cap for applications where V may disappear intermittently for DD short periods of time ...
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TABLE RESET, AND BATTERY BACKUP OPERATION SUMMARY (Shaded Row is same as X1227 operation) (Continued) BSW SWITCHOVER MODE SBIB BIT BIT VOLTAGE Standard Mode, V TRIP Legacy Mode, V ...
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Alarm Operation Examples Below are examples of both Single Event and periodic Interrupt Mode alarms. EXAMPLE 1 Alarm 0 set with single interrupt (IM = “0”) A single alarm will occur on January 1 at 11:30am. A. Set Alarm0 registers ...
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Small Outline Plastic Packages (SOIC) N INDEX 0.25(0.010) H AREA E - SEATING PLANE - -C- α 0.10(0.004) 0.25(0.010 NOTES: 1. Symbols are defined in the ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...