ISL12027IB27AZ Intersil, ISL12027IB27AZ Datasheet - Page 14

• Manufacturer Part Number: ISL12027IB27AZ
• Description: IC RTC/CALENDAR EEPROM 8-SOIC
• Manufacturer: Intersil
• Type: Clock/Calendar/Supervisor/EEPROMr

Specifications of ISL12027IB27AZ

• Memory Size: 4K (512 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Clock Format: HH
• Clock Ic Type: RTC
• Interface Type: I2C, Serial
• Memory Configuration: 512 X 8
• Supply Voltage Range: 2.7V To 5.5V
• Digital Ic Case Style: SOIC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PWR Register: SBIB, BSW, VTS2, VTS1, VTS0
SBIB: Serial Bus Interface (Enable)
The serial bus can be disabled in battery backup mode by
setting this bit to “1”. This will minimize power drain on the
battery. The Serial Interface can be enabled in battery
backup mode by setting this bit to “0” (default is “0”). See
“Power Control Operation” on page 15 and “RESET” on
page 9.
BSW: Power Control Bit
The Power Control bit, BSW, determines the conditions for
switching between V
options:
See “Power Control Operation” on page 15 for more details.
Also see “I
LVR Operation” on page 24 for important details.
VTS2, VTS1, VTS0: V
The ISL12027 is shipped with a default V
(V
This register is a non-volatile with no protection, therefore
any writes to this location can change the default value from
that marked on the package. If not changed with a non-
volatile write, this value will not change over normal
operating and storage conditions. However, ISL12027 has
four (4) additional selectable levels to fit the customers
application. Levels are: 4.64V (default), 4.38V, 3.09V, 2.92V
and 2.63V. The V
and VTS0). See Table 5.
Care should be taken when changing the V
If the V
device will go into RESET and unless V
device will no longer be able to communicate using the I
bus.
Option 1. Standard: Set “BSW = 0” (default for ISL12027A)
Option 2. Legacy /Default Mode: Set “BSW = 1” (default
for ISL12027)
RESET
DTR2
0
0
0
0
1
1
1
1
RESET
DTR REGISTER
) per the “Ordering Information” table on page 2.
TABLE 4. DIGITAL TRIMMING REGISTERS
2
C Communications During Battery Backup and
DTR1
voltage selected is higher than V
0
1
0
1
0
1
0
1
RESET
DD
DTR0
and Backup Battery. There are two
selection is via 3 bits (VTS2, VTS1
RESET
0
0
1
1
0
0
1
1
14
Select Bits
ESTIMATED FREQUENCY
DD
DD
RESET
is increased, the
PPM
+10
+20
+30
threshold
-10
-20
-30
0
0
DD
select bits.
, then the
ISL12027, ISL12027A
2
C
In battery mode, the RESET signal output is asserted LOW
when the VDD voltage supply has dipped below the V
threshold, but the RESET signal output will not return HIGH
until the device is back to V
above V
Device Operation
Writing to the Clock/Control Registers
Changing any of the bits of the clock/control registers
requires the following steps:
Write all 8 bytes to the RTC registers, or one byte to the SR,
or one to five bytes to the control registers. This sequence
starts with a start bit, requires a slave byte of “11011110” and
an address within the CCR and is terminated by a stop bit. A
write to the EEPROM registers in the CCR will initiate a
non-volatile write cycle and will take up to 20ms to complete.
A write to the RTC registers (SRAM) will require much
shorter cycle time (t = t
no effect. The RWEL bit is reset by the completion of a write
to the CCR, so the sequence must be repeated to again
initiate another change to the CCR contents. If the sequence
is not completed for any reason (by sending an incorrect
number of bits or sending a start instead of a stop, for
example) the RWEL bit is not reset and the device remains
in an active mode. Writing all zeros to the status register
resets both the WEL and RWEL bits. A read operation
occurring between any of the previous operations will not
interrupt the register write operation.
Alarm Operation
Since the alarm works as a comparison between the alarm
registers and the RTC registers, it is ideal for notifying a host
processor of a particular time event and trigger some action as
a result. The host can be notified by polling the Status Register
(SR) Alarm bits. These two volatile bits (AL1 for Alarm 1 and
AL0 for Alarm 0), indicate if an alarm has happened. The AL1
and AL0 bits in the status register are reset by the falling edge
of the eighth clock of status register read.
1. Write a 02h to the Status Register to set the Write Enable
2. Write a 06h to the Status Register to set both the Register
VTS2
Latch (WEL). This is a volatile operation, so there is no
delay after the write. (Operation preceded by a start and
ended with a stop).
Write Enable Latch (RWEL) and the WEL bit. This is also
a volatile cycle. The zeros in the data byte are required.
(Operation proceeded by a start and ended with a stop).
0
0
0
0
1
RESET
VTS1
threshold.
0
0
1
1
0
BUF
VTS0
TABLE 5.
). Writes to undefined areas have
0
1
0
1
0
DD
mode even the V
V
4.64V
4.38V
3.09V
2.92V
2.63V
RESET
DD
August 12, 2010
voltage is
RESET
FN8232.8