ISL12027IV27Z Intersil, ISL12027IV27Z Datasheet - Page 26

• Manufacturer Part Number: ISL12027IV27Z
• Description: IC RTC/CAL EEPROM 2.7V 8-TSSO
• Manufacturer: Intersil
• Type: Clock/Calendar/Supervisor/EEPROMr

Specifications of ISL12027IV27Z

• Memory Size: 4K (512 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-TSSOP
• Bus Type: Serial (I2C)
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Pin Count: 8
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Alarm Operation Examples
Following are examples of both Single Event and periodic
Interrupt Mode alarms.
EXAMPLE 1
Alarm 0 set with single interrupt (IM=”0”)
A single alarm will occur on January 1 at 11:30am.
A. Set Alarm 0 registers as follows:
B. Also the AL0E bit must be set as follows:
REGISTER
REGISTER
CONTROL
ALARM0
MOA0
DWA0
MNA0
HRA0
SCA0
DTA0
INT
7 6 5 4 3 2 1 0 HEX
0 0 0 0 0 0 0 0
1 0 1 1 0 0 0 0
1 0 0 1 0 0 0 1
1 0 0 0 0 0 0 1
1 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0 HEX
0 0 1 0 0 0 0 0
BIT
BIT
26
B0h Minutes set to 30,
00h Seconds disabled
91h Hours set to 11,
81h Date set to 1,
81h Month set to 1,
00h Day of week
x0h Enable Alarm
enabled
enabled
enabled
enabled
disabled
DESCRIPTION
DESCRIPTION
ISL12027, ISL12027A
After these registers are set, an alarm will be generated when
the RTC advances to exactly 11:30am on January 1 (after
seconds changes from 59 to 00) by setting the AL0 bit in the
status register to “1”.
EXAMPLE 2
Pulsed interrupt once per minute (IM = ”1”)
Interrupts at one minute intervals when the seconds register
is at 30s.
A. Set Alarm 0 registers as follows:
B. Set the Interrupt register as follows:
Note that the status register AL0 bit will be set each time the
alarm is triggered, but does not need to be read or cleared.
REGISTER
REGISTER
CONTROL
ALARM0
DWA0
MNA0
MOA0
SCA0
HRA0
DTA0
INT
7 6 5 4 3 2 1 0 HEX
1 0 1 0 0 0 0 0 x0h Enable Alarm and Int
7 6 5 4 3 2 1 0 HEX
1 0 1 1 0 0 0 0 B0h Seconds set to 30,
0 0 0 0 0 0 0 0 00h Minutes disabled
0 0 0 0 0 0 0 0 00h Hours disabled
0 0 0 0 0 0 0 0 00h Date disabled
0 0 0 0 0 0 0 0 00h Month disabled
0 0 0 0 0 0 0 0 00h Day of week disabled
BIT
BIT
Mode
enabled
DESCRIPTION
DESCRIPTION
August 12, 2010
FN8232.8