ISL12028IB27Z-T Intersil, ISL12028IB27Z-T Datasheet - Page 17

• Manufacturer Part Number: ISL12028IB27Z-T
• Description: IC RTC/CALENDAR EEPROM 14-SOIC
• Manufacturer: Intersil
• Type: Clock/Calendar/Supervisor/EEPROMr

Specifications of ISL12028IB27Z-T

• Memory Size: 4K (512 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Bus Type: Serial (I2C)
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISL12028IB27Z-TTR

V
The Legacy Mode power control conditions are illustrated in
Figure 15.
Power On Reset
Application of power to the ISL12028 activates a Power On
Reset Circuit that pulls the RESET pin active. This signal
provides several benefits.
When V
typically 250ms the circuit releases RESET, allowing the
system to begin operation. Recommended slew rate is
between 0.2V/ms and 50V/ms.
NOTE: If the V
minimum of 1.8V and the V
to V
I
power will need to be cycled to 0V together to allow normal
operation again.
Watchdog Timer Operation
The watchdog timer time-out period is selectable. By writing
a value to WD1 and WD0, the Watchdog timer can be set
to 3 different time-out periods or off. When the Watchdog
timer is set to off, the Watchdog circuit is configured for low
power operation. See Table 8.
Watchdog Timer Restart
The Watchdog Timer is started by a falling edge of SDA
when the SCL line is high (START condition). The start
signal restarts the Watchdog timer counter, resetting the
2
DD
C communications will not operate. The V
- It prevents the system microprocessor from starting to
- It prevents the processor from operating prior to
- It allows time for an FPGA to download its configuration
- It prevents communication to the EEPROM, greatly
V
BAT
FIGURE 15. BATTERY SWITCHOVER IN LEGACY MODE
DD
operate with insufficient voltage.
stabilization of the oscillator.
prior to initialization of the circuit.
reducing the likelihood of data corruption on power-up.
WD1
> V
1
1
0
0
voltage, then the RESET output may stay low and the
DD
BAT
TABLE 8. WATCHDOG TIMER OPERATION
exceeds the device V
+V
BAT
BATHYS
OFF
WD0
voltage drops below the data sheet
1
0
1
0
V
DD
DD
17
power cycles to 0V then back
RESET
VOLTAGE
DURATION
threshold value for
disabled
250ms
750ms
1.75s
BAT
and V
ON
ISL12028, ISL12028A
DD
IN
period of the counter back to the maximum. If another
START fails to be detected prior to the Watchdog timer
expiration, then the RESET pin becomes active for one reset
time out period. In the event that the start signal occurs
during a reset time out period, the start will have no effect.
When using a single START to refresh Watchdog timer, a
STOP condition should be followed to reset the device back
to stand-by mode (see Figure 3).
In battery mode, the Watchdog timer function is disabled.
Low Voltage Reset (LVR) Operation
When a power failure occurs, a voltage comparator
compares the level of the V
voltage (V
below V
V
V
Power-up and power-down waveforms are shown in
Figure 4 on page 7. The LVR circuit is to be designed so the
RESET signal is valid down to V
When the LVR signal is active, unless the part has been
switched into the battery mode, the completion of an
in-progress non-volatile write cycle is unaffected, allowing a
non-volatile write to continue as long as possible (down to
the Reset Valid Voltage). The LVR signal, when active, will
terminate any in-progress communications to the device and
prevents new commands from disrupting any current write
operations. See “I
Backup and LVR Operation” on page 25.
In battery mode, the RESET signal output is asserted LOW
when the V
threshold. The RESET signal output will not return HIGH
until the device is back to V
above V
Serial Communication
The device supports the I
CLOCK AND DATA
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are reserved for
indicating start and stop conditions (see Figure 16).
START CONDITION
All commands are preceded by the start condition, which is a
HIGH to LOW transition of SDA when SCL is HIGH. The
device continuously monitors the SDA and SCL lines for the
start condition and will not respond to any command until
this condition has been met (see Figure 17).
STOP CONDITION
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA when SCL is
HIGH. The stop condition is also used to place the device
into the Standby power mode after a read sequence. A stop
DD
RESET
line rises above V
, then the RESET output will remain asserted low.
RESET
RESET
RESET
DD
. The reset pulse will time-out 250ms after the
voltage supply has dipped below the V
threshold.
), then generates a RESET pulse if it is
2
C Communications During Battery
RESET
2
C bidirectional serial bus protocol.
DD
DD
. If the V
mode even the V
line versus a preset threshold
DD
= 1.0V.
DD
remains below
November 30, 2010
DD
voltage is
RESET
FN8233.9