ISL12029IB30AZ Intersil, ISL12029IB30AZ Datasheet - Page 20

• Manufacturer Part Number: ISL12029IB30AZ
• Description: IC RTC/CALENDAR EEPROM 14-SOIC
• Manufacturer: Intersil
• Type: Clock/Calendar/Supervisor/EEPROMr

Specifications of ISL12029IB30AZ

• Memory Size: 4K (512 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Write Operations
Byte Write
For a write operation, the device requires the Slave Address
Byte and the Word Address Bytes. This gives the master
access to any one of the words in the array or CCR. (Note:
Prior to writing to the CCR, the master must write a 02h, then
06h to the status register in two preceding operations to
enable the write operation. See “Writing to the Clock/Control
Registers” on page 15. Upon receipt of each address byte,
the ISL12029 responds with an acknowledge. After receiving
both address bytes the ISL12029 awaits the eight bits of
data. After receiving the 8 data bits, the ISL12029 again
responds with an acknowledge. The master then terminates
the transfer by generating a stop condition. The ISL12029
then begins an internal write cycle of the data to the
non-volatile memory. During the internal write cycle, the
device inputs are disabled, so the device will not respond to
any requests from the master. The SDA output is at high
impedance (see Figure 20).
A write to a protected block of memory is ignored, but will still
receive an acknowledge. At the end of the write command,
the ISL12029 will not initiate an internal write cycle, and will
continue to ACK commands.
Byte writes to all of the non-volatile registers are allowed,
except the DWAn registers which require multiple byte writes
or page writes to trigger non-volatile writes. See “Device
Operation” on page 15 for more information.
Page Write
The ISL12029 has a page write operation. It is initiated in the
same manner as the byte write operation; but instead of
terminating the write cycle after the first data byte is transferred,
the master can transmit up to 15 more bytes to the memory
array and up to 7 more bytes to the clock/control registers. The
ADDRESS POINTER ENDS
6 BYTES
FIGURE 21. WRITING 12 BYTES TO A 16-BYTE MEMORY PAGE STARTING AT ADDRESS 10
SIGNALS FROM
SIGNALS FROM
ADDRESS = 5
AT ADDR = 5
THE MASTER
THE SLAVE
SDA BUS
20
A
R
S
T
T
1
FIGURE 20. BYTE WRITE SEQUENCE
ADDRESS
ISL12029, ISL12029A
SLAVE
1
1
1
0
A
C
K
0 0 0 0 0 0 0
ADDRESS 1
WORD
RTC registers require a page write (8 bytes), individual register
writes are not allowed. (Note: Prior to writing to the CCR, the
master must write a 02h, then 06h to the status register in two
preceding operations to enable the write operation. See
“Writing to the Clock/Control Registers” on page 15.)
After the receipt of each byte, the ISL12029 responds with
an acknowledge, and the address is internally incremented
by one. The address pointer remains at the last address byte
written. When the counter reaches the end of the page, it
“rolls over” and goes back to the first address on the same
page. This means that the master can write 16 bytes to a
memory array page or 8 bytes to a CCR section starting at
any location on that page. For example, if the master begins
writing at location 10 of the memory and loads 15 bytes, then
the first 6 bytes are written to addresses 10 through 15, and
the last 6 bytes are written to columns 0 through 5.
Afterwards, the address counter would point to location 6 on
the page that was just written. If the master supplies more
than the maximum bytes in a page, then the previously
loaded data is over-written by the new data, one byte at a
time (refer to Figure 21).The master terminates the Data
Byte loading by issuing a stop condition, which causes the
ISL12029 to begin the non-volatile write cycle. As with the
byte write operation, all inputs are disabled until completion
of the internal write cycle. Refer to Figure 22 for the address,
acknowledge and data transfer sequence.
Stops and Write Modes
Stop conditions that terminate write operations must be sent by
the master after sending at least 1 full data byte and it’s
associated ACK signal. If a stop is issued in the middle of a
data byte, or before 1 full data byte + ACK is sent, then the
ISL12029 resets itself without performing the write. The
contents of the array are not affected.
ADDRESS
A
C
K
10
ADDRESS 0
WORD
A
C
K
6 BYTES
DATA
ADDRESS
A
C
K
15
S
O
P
T
December 16, 2010
FN6206.10