X1226S8 Intersil, X1226S8 Datasheet - Page 6

• Manufacturer Part Number: X1226S8
• Description: IC RTC CLNDR OUTFREQ 4K EE 8SOIC
• Manufacturer: Intersil
• Type: Clock/Calendar/EEPROMr

Specifications of X1226S8

• Memory Size: 4K (512 x 8)
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

once reaching the end of a section, will wrap around to
the start of the section. A read or write can begin at any
address in the CCR.
It is not necessary to set the RWEL bit prior to writing
the status register. Section 5 (status register) supports
a single byte read or write only. Continued reads or
writes from this section terminates the operation.
The state of the CCR can be read by performing a ran-
dom read at any address in the CCR at any time. This
returns the contents of that register location. Additional
Table 1. Clock/Control Memory Map
000D
000C
Addr.
003F
0037
0036
0035
0034
0033
0032
0031
0030
0013
0012
0011
0010
000F
000E
000B
000A
0009
0008
0007
0006
0005
0004
0003
0002
0001
0000
(EEPROM)
(EEPROM)
(EEPROM)
(SRAM)
Control
Alarm1
Alarm0
Status
Type
RTC
DWA1
DWA0
MOA1
MNA1
MOA0
MNA0
YRA1
DTA1
HRA1
SCA1
YRA0
DTA0
HRA0
SCA0
Name
Y2K1
Y2K0
DTR
Y2K
ATR
Reg
DW
MO
INT
HR
MN
SR
YR
DT
SC
BL
6
EDW1
EMO1
EMN1
EDW0
EMO0
EMN0
EDT1
EHR1
ESC1
EDT0
EHR0
ESC0
BAT
Y23
BP2
MIL
IM
0
0
0
0
0
0
0
0
0
0
7
A1M22
A0M22
A1S22
A0S22
AL1E
M22
BP1
AL1
Y22
S22
Unused - Default = RTC Year value (No EEPROM) - Future expansion
Unused - Default = RTC Year value (No EEPROM) - Future expansion
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A1Y2K21
A0Y2K21
A1D21
A1H21
A1M21
A0D21
A0H21
A0M21
Y2K21
A1S21
A0S21
ATR5
AL0E
M21
AL0
Y21
D21
H21
S21
BP0
5
0
0
0
0
0
0
0
A1Y2K20
A0Y2K20
A1G20
A1M20
A0M20
Y2K20
A1D20
A1H20
A1S20
A0G20
A0D20
A0H20
A0S20
ATR4
X1226
G20
M20
FO1
Y20
D20
H20
S20
0
0
4
0
0
0
0
Bit
registers are read by performing a sequential read.
The read instruction latches all Clock registers into a
buffer, so an update of the clock does not change the
time being read. A sequential read of the CCR will not
result in the output of data from the memory array. At
the end of a read, the master supplies a stop condition
to end the operation and free the bus. After a read of
the CCR, the address remains at the previous address
+1 so the user can execute a current address read of
the CCR and continue reading the next Register.
A1Y2K13
A0Y2K13
A1G13
A1D13
A1H13
A1M13
A0G13
A0D13
A0H13
A0M13
Y2K13
A1S13
A0S13
ATR3
M13
FO0
Y13
G13
D13
H13
S13
3
0
0
0
0
0
0
A1M12
A0M12
A1G12
A1D12
A1H12
A1S12
A0G12
A0D12
A0H12
A0S12
RWEL
DTR2
ATR2
DY2
G12
M12
DY2
DY2
Y12
D12
H12
S12
X
2
0
0
0
0
A1G11
A1M11
A0G11
A0M11
A1D11
A1H11
A1S11
A0D11
A0H11
A0S11
DTR1
ATR1
WEL
DY1
G11
D11
H11
M11
DY1
DY1
Y11
S11
X
0
0
0
0
1
0 (optional)
A1Y2K10
A0Y2K10
A1M10
A0M10
Y2K10
A1G10
A1D10
A1H10
A1S10
A0G10
A0D10
A0H10
A0S10
RTCF
DTR0
ATR0
DY0
G10
M10
DY0
DY0
Y10
D10
H10
S10
X
0
Range
19/20
19/20
19/20
0-99
1-12
1-31
0-23
0-59
0-59
1-12
1-31
0-23
0-59
0-59
1-12
1-31
0-23
0-59
0-59
0-6
0-6
0-6
May 8, 2006
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FN8098.3