DS14285SN Maxim Integrated Products, DS14285SN Datasheet - Page 11

• Manufacturer Part Number: DS14285SN
• Description: IC RTC W/NV RAM CNTRL IND 24SOIC
• Manufacturer: Maxim Integrated Products
• Type: Clock/Calendar/NVSRAMr

Specifications of DS14285SN

• Memory Size: 114B
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DS14285/DS14287
REGISTER B
MSB
LSB
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SET
PIE
AIE
UIE
SQWE
DM
24/12
DSE
SET - When the SET bit is a 0, the update transfer functions normally by advancing the counts once per
second. When the SET bit is written to a 1, any update transfer is inhibited and the program can initialize
the time and calendar bytes without an update occurring in the midst of initializing. Read cycles can be
executed in a similar manner. SET is a read/write bit that is not modified by
or internal functions
RESET
of the DS14285/DS14287.
PIE - The periodic interrupt enable PIE bit is a read/write bit which allows the Periodic Interrupt Flag
(PF) bit in Register C to drive the
pin low. When the PIE bit is set to 1, periodic interrupts are
IRQ
generated by driving the
pin low at a rate specified by the RS3-RS0 bits of Register A. A 0 in the
IRQ
PIE bit blocks the
output from being driven by a periodic interrupt, but the Periodic Flag (PF) bit is
IRQ
still set at the periodic rate. PIE is not modified by any internal DS14285/DS14287 functions, but is
cleared to 0 on
.
RESET
AIE - The Alarm Interrupt Enable (AIE) bit is a read/write bit which, when set to a 1, permits the Alarm
Flag (AF) bit in register C to assert
. An alarm interrupt occurs for each second that the 3 time bytes
IRQ
equal the 3 alarm bytes including a “don’t care” alarm code of binary 11XXXXXX. When the AIE bit is
set to 0, the AF bit does not initiate the
signal. The
pin clears AIE to 0. The internal
IRQ
RESET
functions of the DS14285/DS14287 do not affect the AIE bit.
UIE - The Update Ended Interrupt Enable (UIE) bit is a read/write that enables the Update End Flag (UF)
bit in Register C to assert
. The
pin going low or the SET bit going high clears to UIE bit.
IRQ
RESET
SQWE - When the Square Wave Enable (SQWE) bit is set to a 1, a square wave signal at the frequency
set by the rate-selection bits RS3 through RS0 is driven out on a SQW pin. When the SQWE bit is set to
0, the SQW pin is held low; the state of SQWE is cleared by the
pin. SQWE is a read/write bit.
RESET
DM - The Data Mode (DM) bit indicates whether time and calendar information is in binary or BCD
format. The DM bit is set by the program to the appropriate format and can be read as required. This bit is
not modified by internal functions or
. A one in DM signifies binary data while a 0 in DM
RESET
specifies Binary Coded Decimal (BCD) data.
24/12 - The 24/12 control bit establishes the format of the hours byte. A 1 indicates the 24-hour mode and
a 0 indicates the 12-hour mode. This bit is read/write and is not affected by internal functions of
.
RESET
DSE - The Daylight Savings Enable (DSE) bit is a read/write bit which enables two special updates when
DSE is set to 1. On the first Sunday in April the time increments from 1:59:59 AM to 3:00:00 AM. On
the last Sunday in October when the time first reaches 1:59:59 AM it changes to 1:00:00 AM. These
special updates do not occur when the DSE bit is a 0. This bit is not affected by internal functions or
.
RESET
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