DS14285SN Maxim Integrated Products, DS14285SN Datasheet - Page 5

• Manufacturer Part Number: DS14285SN
• Description: IC RTC W/NV RAM CNTRL IND 24SOIC
• Manufacturer: Maxim Integrated Products
• Type: Clock/Calendar/NVSRAMr

Specifications of DS14285SN

• Memory Size: 114B
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

that
time
DS14285/DS14287 on power-up has timed out. When
following occurs:
In a typical application
and out of power fail without affecting any of the control registers.
RAM.
V
internal switch to power an external RAM.
DS14285 Only
X1, X2 - Connections for a standard 32.768 kHz quartz crystal. The internal oscillator circuitry is
designed for operation with a crystal having a specified load capacitance (CL) of 6 pF. The crystal is
connected directly to the X1 and X2 pins. There is no need for external capacitors or resistors. Note: X1
and X2 are very high impedance nodes. It is recommended that they and the crystal be guard–ringed with
ground and that high frequency signals be kept away from the crystal area. For more information on
crystal selection and crystal layout considerations, please consult Application Note 58, “Crystal
Considerations with Dallas Real Time Clocks.”
V
section for considerations in selecting the size of the external energy source
CEI
CEO
RESET
RESET
CEO
CEO
CCO
BAT
RESET
(External RAM Chip Enable Input, active low) -
will be forced to an inactive level regardless of
(External RAM Chip Enable Output, active low) - When V
will reflect
– Battery input for any standard 3-volt lithium cell or other energy source. See the Power-Up/Down
RESET
(External RAM Power Supply Output) - V
CEI
pin can be held low for a time in order to allow the power supply to stabilize. The amount of time
(Reset Input) - The
is internally pulled up with a 50kΩ resistor.
is held low is dependent on the application. However, if
is low should exceed 200 ms to make sure that the internal timer that controls the
A. Periodic Interrupt Enable (PEI) bit is cleared to 0.
B. Alarm Interrupt Enable (AIE) bit is cleared to 0.
C. Update Ended Interrupt Flag (UF) bit is cleared to 0.
D. Interrupt Request Status Flag (IRQF) bit is cleared to 0.
E. Periodic Interrupt Flag (PF) bit is cleared to 0.
F. The device is not accessible until
G. Alarm Interrupt Flag (AF) bit is cleared to 0.
H.
I. Square Wave Output Enable (
J. Update Ended Interrupt Enable (UIE) is cleared to 0.
K.
CEI
CEO
IRQ
provided the
pin is in the high impedance state.
RESET
is driven high.
RESET
can be connected to V
RESET
pin has no effect on the clock, calendar, or RAM. On power-up the
is at a logic high. When V
SQWE
5 of 26
RESET
CCO
CEI
CC
) bit is cleared to 0.
. This connection will allow the DS14287 to go in
RESET
.
provides the higher of V
CEI
is returned high.
should be driven low to enable the external
is low and V
CC
CC
is greater than 4.25 volts (typical),
RESET
is less than 4.25 volts (typical),
CC
is used on power-up, the
is above 4.25 volts, the
CC
or V
BAT
through an