DS14285SN Maxim Integrated Products, DS14285SN Datasheet - Page 12

• Manufacturer Part Number: DS14285SN
• Description: IC RTC W/NV RAM CNTRL IND 24SOIC
• Manufacturer: Maxim Integrated Products
• Type: Clock/Calendar/NVSRAMr

Specifications of DS14285SN

• Memory Size: 114B
• Time Format: HH:MM:SS (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

REGISTER C
MSB
IRQF - The Interrupt Request Flag (IRQF) bit is set to a 1 when one or more of the following are true:
PF = PIE = 1
AF = AIE = 1
UF = UIE = 1
That is, IRQF = PF • PIE + AF • AIE + UF • UIE.
Any time the IRQF bit is a 1, the
by the program or when the
PF - The Periodic Interrupt Flag (PF) is a read-only bit which is set to a 1 when an edge is detected on the
selected tap of the divider chain. The RS3 through RS0 bits establish the periodic rate. PF is set to a 1
independent of the state of the PIE bit. When both PF and PIE are 1s, the
the IRQF bit. The PF bit is cleared by a
AF - A 1 in the Alarm Interrupt Flag (AF) bit indicates that the current time has matched the alarm time.
If the AIE bit is also a 1, the
read of Register C will clear AF.
UF - The Update Ended Interrupt Flag (UF) bit is set after each update cycle. When the UIE bit is set to
1, the 1 in UF causes the IRQF bit to be a 1 which will assert the
Register C or a
BIT 0 THROUGH BIT 3 - These are unused bits of the status Register C. These bits always read 0 and
cannot be written.
REGISTER D
MSB
VRT - The Valid RAM and Time (VRT) bit indicates the condition of the internal battery (the battery
connected to the V
writable and should always be a 1 when read. If a 0 is ever present, an exhausted internal lithium energy
source is indicated and both the contents of the RTC data and RAM data are questionable. This bit is
unaffected by
BIT 6 THROUGH BIT 0 - The remaining bits of Register D are not usable. They cannot be written and,
when read, they will always read 0.
BIT 7
BIT 7
IRQF
VRT
RESET
RESET
BIT 6
BIT 6
PF
0
BAT
.
.
pin in the case of the DS14285S, DS14285, and the DS14285Q). This bit is not
RESET
BIT 5
BIT 5
IRQ
AF
0
IRQ
pin will go low and a one will appear in the IRQF bit. A
pin is low.
pin is driven low. All flag bits are cleared after Register C is read
RESET
BIT 4
BIT 4
UF
0
or a software read of Register C.
12 of 26
BIT 3
BIT 3
0
0
BIT 2
BIT 2
IRQ
0
0
IRQ
pin. UF is cleared by reading
signal is active and will set
BIT 1
BIT 1
0
0
RESET
BIT 0
BIT 0
0
0
LSB
LSB
or a