AD7663ASTZ Analog Devices Inc, AD7663ASTZ Datasheet - Page 11

• Manufacturer Part Number: AD7663ASTZ
• Description: IC ADC 16BIT CMOS 48-LQFP
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of AD7663ASTZ

• Data Interface: Serial, Parallel
• Number Of Bits: 16
• Sampling Rate (per Second): 250k
• Number Of Converters: 1
• Power Dissipation (max): 41mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Resolution (bits): 16bit
• Sampling Rate: 250kSPS
• Input Channel Type: Differential
• Supply Voltage Range - Analog: 4.75V To 5.25V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-AD7663CBZ - BOARD EVALUATION FOR AD7663
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

REV. B
TPC 14. Power-Down Operating Currents vs. Temperature
100000
10000
0.001
TPC 15. +FS, Offset, and –FS vs. Temperature
1000
–10
0.01
TPC 13. Operating Currents vs. Sample Rate
100
500
450
400
350
300
250
200
150
100
–2
–8
10
–4
–6
0.1
10
50
8
6
4
2
0
1
0
–55
–55
1
+FS
–35
–35
–FS
10
–15
–15
5
100
SAMPLING RATE – SPS
TEMPERATURE – C
TEMPERATURE – C
OFFSET
5
25
1000
25
45
45
10000
65
AVDD
DVDD
OVDD
65
85
OVDD
100000
DVDD
85
105
AVDD
1000000
125
105
–11–
CIRCUIT INFORMATION
The AD7663 is a fast, low power, single-supply, precise 16-bit
analog-to-digital converter (ADC). The AD7663 is capable of
converting 250,000 samples per second (250 kSPS) and allows
power saving between conversions. When operating at 100 SPS,
for example, it consumes typically only 15 µW. This feature
makes the AD7663 ideal for battery-powered applications.
The AD7663 provides the user with an on-chip track-and-hold,
successive approximation ADC that does not exhibit any pipeline
or latency, making it ideal for multiple multiplexed channel
applications.
It is specified to operate with both bipolar and unipolar input
ranges by changing the connection of its input resistive scaler.
The AD7663 can be operated from a single 5 V supply and can be
interfaced to either 5 V or 3 V digital logic. It is housed in a 48-lead
LQFP package or a 48-lead LFCSP package that combines space
savings and flexible configurations as either serial or parallel inter-
face. The AD7663 is pin-to-pin compatible with the AD7660.
CONVERTER OPERATION
The AD7663 is a successive approximation analog-to-digital
converter based on a charge redistribution DAC. Figure 3 shows
the simplified schematic of the ADC. The input analog signal is
first scaled down and level shifted by the internal input resistive
scaler, which allows both unipolar ranges (0 V to 2.5 V, 0 V to 5 V,
and 0 V to 10 V) and bipolar ranges (±2.5 V, ±5 V, and ±10 V).
The output voltage range of the resistive scaler is always 0 V to
2.5 V. The capacitive DAC consists of an array of 16 binary
weighted capacitors and an additional “LSB” capacitor. The
comparator’s negative input is connected to a “dummy” capacitor
of the same value as the capacitive DAC array.
During the acquisition phase, the common terminal of the array
tied to the comparator’s positive input is connected to AGND
via SW
of the resistive scaler. Thus, the capacitor array is used as a
sampling capacitor and acquires the analog signal. Similarly, the
dummy capacitor acquires the analog signal on INGND input.
When the acquisition phase is complete and the CNVST input
goes or is LOW, a conversion phase is initiated. When the conver-
sion phase begins, SW
array and the dummy capacitor are then disconnected from the
inputs and connected to the REFGND input. Therefore, the differ-
ential voltage between the output of the resistive scaler and INGND
captured at the end of the acquisition phase is applied to the
comparator inputs, causing the comparator to become unbalanced.
By switching each element of the capacitor array between
REFGND or REF, the comparator input varies by binary
weighted voltage steps (V
control logic toggles these switches, starting with the MSB first,
in order to bring the comparator back into a balanced condition.
After the completion of this process, the control logic generates
the ADC output code and brings the BUSY output LOW.
A
. All independent switches are connected to the output
A
and SW
REF
/2, V
B
are opened first. The capacitor
REF
/4 . . . V
REF
AD7663
/65,536). The