MAX1184ECM+TD Maxim Integrated Products, MAX1184ECM+TD Datasheet - Page 11

• Manufacturer Part Number: MAX1184ECM+TD
• Description: IC ADC 10BIT 20MSPS DL 48-TQFP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1184ECM+TD

• Number Of Bits: 10
• Sampling Rate (per Second): 20M
• Data Interface: Parallel
• Number Of Converters: 2
• Power Dissipation (max): 150mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP Exposed Pad, 48-eTQFP, 48-HTQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX1184 uses a 9-stage, fully-differential
pipelined architecture (Figure 1) that allows for high-
speed conversion while minimizing power consump-
tion. Samples taken at the inputs move progressively
through the pipeline stages every half clock cycle.
Counting the delay through the output latch, the clock-
cycle latency is five clock cycles.
1.5-bit (2-comparator) flash ADCs convert the held-
input voltages into a digital code. The digital-to-analog
Figure 1. Pipelined Architecture—Stage Blocks
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
V
INB
T/H
FLASH
ADC
1.5 BITS
STAGE 1
T/H
______________________________________________________________________________________
Internal Reference and Parallel Outputs
DAC
Detailed Description
DIGITAL CORRECTION LOGIC
V
V
Σ
INA
INB
D9B–D0B
STAGE 2
= INPUT VOLTAGE BETWEEN INA+ AND INA- (DIFFERENTIAL OR SINGLE-ENDED)
= INPUT VOLTAGE BETWEEN INB+ AND INB- (DIFFERENTIAL OR SINGLE-ENDED)
10
x2
V
OUT
STAGE 8
2-BIT FLASH
STAGE 9
ADC
V
IN
converters (DACs) convert the digitized results back
into analog voltages, which are then subtracted from
the original held input signals. The resulting error sig-
nals are then multiplied by two and the residues are
passed along to the next pipeline stages, where the
process is repeated until the signals have been
processed by all nine stages. Digital error correction
compensates for ADC comparator offsets in each of
these pipeline stages and ensures no missing codes.
V
INB
T/H
FLASH
ADC
1.5 BITS
STAGE 1
T/H
DAC
DIGITAL CORRECTION LOGIC
Σ
D9B–D0B
STAGE 2
10
x2
V
OUT
STAGE 8
2-BIT FLASH
STAGE 9
ADC
11