MAX1184ECM+TD Maxim Integrated Products, MAX1184ECM+TD Datasheet - Page 14

• Manufacturer Part Number: MAX1184ECM+TD
• Description: IC ADC 10BIT 20MSPS DL 48-TQFP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1184ECM+TD

• Number Of Bits: 10
• Sampling Rate (per Second): 20M
• Data Interface: Parallel
• Number Of Converters: 2
• Power Dissipation (max): 150mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP Exposed Pad, 48-eTQFP, 48-HTQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The output coding can be chosen to be either straight
offset binary or two’s complement (Table 1) controlled
by a single pin (T/B). Pull T/B low to select offset binary
and high to activate two’s complement output coding.
The capacitive load on the digital outputs D0A–D9A
and D0B–D9B should be kept as low as possible
(<15pF) to avoid large digital currents that could feed
back into the analog portion of the MAX1184, thereby
degrading its dynamic performance. Using buffers on
the digital outputs of the ADCs can further isolate the
digital outputs from heavy capacitive loads. To further
improve the dynamic performance of the MAX1184,
small-series resistors (e.g., 100Ω) may be added to the
digital output paths close to the MAX1184.
Figure 4 displays the timing relationship between out-
put enable and data output valid as well as power-
down/wake-up and data output valid.
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
Table 1. MAX1184 Output Codes For Differential Inputs
*V
14
Figure 4. Output Timing Diagram
D9A–D0A
D9B–D0B
REF
OUTPUT
OUTPUT
DIFFERENTIAL INPUT
______________________________________________________________________________________
OE
= V
-V
-V
V
- V
REFP
V
REF
VOLTAGE*
REF
REF
REF
REF
x 511/512
x 511/512
x 512/512
- V
HIGH-Z
HIGH-Z
x 1/512
0
x 1/512
REFN
t
ENABLE
VALID DATA
VALID DATA
- FULL SCALE + 1 LSB
+FULL SCALE - 1LSB
t
DISABLE
DIFFERENTIAL
- FULL SCALE
Bipolar Zero
+ 1 LSB
- 1 LSB
INPUT
HIGH-Z
HIGH-Z
The MAX1184 offers two power-save modes—sleep and
full power-down mode. In sleep mode (SLEEP = 1), only
the reference bias circuit is active (both ADCs are dis-
abled), and current consumption is reduced to 2.8mA.
To enter full power-down mode, pull PD high. With OE
simultaneously low, all outputs are latched at the last
value prior to the power down. Pulling OE high forces
the digital outputs into a high-impedance state.
Figure 5 depicts a typical application circuit containing
two single-ended to differential converters. The internal
reference provides a V
ing purposes. The input is buffered and then split to a
voltage follower and inverter. One lowpass filter per ADC
suppresses some of the wideband noise associated with
high-speed op amps follows the amplifiers. The user may
select the R
formance, to suit a particular application. For the applica-
tion in Figure 5, a R
capacitive load to prevent ringing and oscillation. The
22pF C
STRAIGHT OFFSET
11 1111 1111
10 0000 0001
10 0000 0000
01 1111 1111
00 0000 0001
00 0000 0000
IN
BINARY
T/B = 0
capacitor acts as a small bypassing capacitor.
ISO
Applications Information
and C
ISO
IN
DD
values to optimize the filter per-
/2 output voltage for level-shift-
of 50Ω is placed before the
Power-Down (PD) and
Sleep (SLEEP) Modes
TWO’S COMPLEMENT
01 1111 1111
00 0000 0001
00 0000 0000
11 1111 1111
10 0000 0001
10 0000 0000
T/B = 1