AD7685CRM Analog Devices Inc, AD7685CRM Datasheet - Page 16

• Manufacturer Part Number: AD7685CRM
• Description: IC ADC 16BIT PSEUDO-DIFF 10-MSOP
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of AD7685CRM

• Design Resources: Parametric Measurement Unit and Supporting Components for PAD Appls Using AD5522 and AD7685 (CN0104) Integrated Device Power Supply for PAD with Output Voltage Range 0 V to 25 V (CN0130)
• Number Of Bits: 16
• Sampling Rate (per Second): 250k
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 15mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP (0.118", 3.00mm Width)
• For Use With: EVAL-AD7685CBZ - BOARD EVAL FOR AD7685
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD7685
DRIVER AMPLIFIER CHOICE
Although the AD7685 is easy to drive, the driver amplifier
needs to meet the following requirements:
• The noise generated by the driver amplifier needs to be kept
• For ac applications, the driver should have a THD
• For multichannel, multiplexed applications, the driver
Table 9. Recommended Driver Amplifiers
Amplifier
ADA4841-x
AD8605, AD8615
AD8655
OP184
AD8021
AD8022
AD8519
AD8031
as low as possible to preserve the SNR and transition noise
performance of the AD7685. Note that the AD7685 has a
noise much lower than most of the other 16-bit ADCs and,
therefore, can be driven by a noisier amplifier to meet a given
system noise specification. The noise coming from the
amplifier is filtered by the AD7685 analog input circuit low-
pass filter made by R
is used. Because the typical noise of the AD7685 is 35 μV
rms, the SNR degradation due to the amplifier is
performance commensurate with the AD7685. Figure 17
shows the AD7685’s THD vs. frequency.
amplifier and the AD7685 analog input circuit must settle a
full-scale step onto the capacitor array at a 16-bit level
(0.0015%). In the amplifier’s data sheet, settling at 0.1% to
0.01% is more commonly specified. This could differ
significantly from the settling time at a 16-bit level and
should be verified prior to driver selection.
where:
f
(2 MHz) or the cutoff frequency of the input filter, if one is
used.
N is the noise gain of the amplifier (for example, 1 in buffer
configuration).
e
nV/√Hz.
SNR
–3dB
N
is the equivalent input noise voltage of the op amp, in
is the input bandwidth in MHz of the AD7685
LOSS
=
20log
Typical Application
Very low noise and low power
5 V single-supply, low power
5 V single-supply, low power
Low power, low noise, and low frequency
Very low noise and high frequency
Very low noise and high frequency
Small, low power and low frequency
High frequency and low power
⎛
⎜
⎜
⎜
⎜
⎝
IN
and C
35
2
+
IN
π
2
or by an external filter, if one
f
35
−
3dB
(
Ne
N
)
2
⎞
⎟
⎟
⎟
⎟
⎠
Rev. B | Page 16 of 28
VOLTAGE REFERENCE INPUT
The AD7685 voltage reference input, REF, has a dynamic input
impedance and should therefore be driven by a low impedance
source with efficient decoupling between the REF and GND
pins, as explained in the Layout section.
When REF is driven by a very low impedance source, for
example, a reference buffer using the
10 μF (X5R, 0805 size) ceramic chip capacitor is appropriate for
optimum performance.
If an unbuffered reference voltage is used, the decoupling value
depends on the reference used. For instance, a 22 μF (X5R,
1206 size) ceramic chip capacitor is appropriate for optimum
performance using a low temperature drift ADR43x reference.
If desired, smaller reference decoupling capacitor values down
to 2.2 μF can be used with a minimal impact on performance,
especially DNL.
POWER SUPPLY
The AD7685 is specified over a wide operating range from
2.3 V to 5.5 V. It has, unlike other low voltage converters, a
noise low enough to design a 16-bit resolution system with low
supply and respectable performance. It uses two power supply
pins: a core supply VDD and a digital input/output interface
supply VIO. VIO allows direct interface with any logic between
1.8 V and VDD. To reduce the number of supplies needed, the
VIO and VDD can be tied together. The AD7685 is independent of
power supply sequencing between VIO and VDD. Additionally,
it is very insensitive to power supply variations over a wide
frequency range, as shown in Figure 31, which represents PSRR
over frequency.
100
110
90
80
70
60
50
40
30
1
10
Figure 31. PSRR vs. Frequency
FREQUENCY (kHz)
VDD = 2.5V
100
VDD = 5V
AD8031
1000
or the AD8605, a
10000