AD7685CRM Analog Devices Inc, AD7685CRM Datasheet - Page 19

• Manufacturer Part Number: AD7685CRM
• Description: IC ADC 16BIT PSEUDO-DIFF 10-MSOP
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of AD7685CRM

• Design Resources: Parametric Measurement Unit and Supporting Components for PAD Appls Using AD5522 and AD7685 (CN0104) Integrated Device Power Supply for PAD with Output Voltage Range 0 V to 25 V (CN0130)
• Number Of Bits: 16
• Sampling Rate (per Second): 250k
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 15mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP (0.118", 3.00mm Width)
• For Use With: EVAL-AD7685CBZ - BOARD EVAL FOR AD7685
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

CS MODE 3-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7685 is connected
to an SPI-compatible digital host having an interrupt input.
The connection diagram is shown in Figure 36, and the
corresponding timing is given in Figure 37.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. SDO is maintained in high impedance until the
completion of the conversion irrespective of the state of CNV.
Prior to the minimum conversion time, CNV could be used to
select other SPI devices, such as analog multiplexers, but CNV
must be returned low before the minimum conversion time and
held low until the maximum conversion time to guarantee the
generation of the BUSY signal indicator. When the conversion
is complete, SDO goes from high impedance to low. With a
pull-up on the SDO line, this transition can be used as an
interrupt signal to initiate the data reading controlled by the
digital host. The AD7685 then enters the acquisition phase and
ACQUISITION
SDI = 1
SDO
CNV
SCK
CONVERSION
Figure 37. CS Mode 3-Wire with BUSY Indicator Serial Interface Timing (SDI High)
t
CONV
t
CNVH
1
Rev. B | Page 19 of 28
t
t
HSDO
DSDO
D15
t
2
CYC
ACQUISITION
D14
powers down. The data bits are then clocked out, MSB first, by
subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge will allow a faster reading
rate provided it has an acceptable hold time. After the optional
17th SCK falling edge, or when CNV goes high, whichever is
earlier, SDO returns to high impedance.
t
3
ACQ
t
VIO
SCKL
t
SCKH
15
SDI
Figure 36. CS Mode 3-Wire with BUSY Indicator
AD7685
t
SCK
CNV
SCK
Connection Diagram (SDI High)
16
D1
SDO
17
D0
VIO
47kΩ
t
DIS
CLK
CONVERT
DATA IN
IRQ
DIGITAL HOST
AD7685