AD7685CRM Analog Devices Inc, AD7685CRM Datasheet - Page 23

• Manufacturer Part Number: AD7685CRM
• Description: IC ADC 16BIT PSEUDO-DIFF 10-MSOP
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of AD7685CRM

• Design Resources: Parametric Measurement Unit and Supporting Components for PAD Appls Using AD5522 and AD7685 (CN0104) Integrated Device Power Supply for PAD with Output Voltage Range 0 V to 25 V (CN0130)
• Number Of Bits: 16
• Sampling Rate (per Second): 250k
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 15mW
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-TFSOP (0.118", 3.00mm Width)
• For Use With: EVAL-AD7685CBZ - BOARD EVAL FOR AD7685
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

CHAIN MODE WITH BUSY INDICATOR
This mode can also be used to daisy chain multiple AD7685s on
a 3-wire serial interface while providing a BUSY indicator. This
feature is useful for reducing component count and wiring
connections, for example, in isolated multiconverter applications or
for systems with a limited interfacing capacity. Data readback is
analogous to clocking a shift register.
A connection diagram example using three AD7685s is shown
in Figure 44, and the corresponding timing is given in Figure 45.
When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the BUSY indicator feature. In this
mode, CNV is held high during the conversion phase and the
subsequent data readback. When all ADCs in the chain have
completed their conversions, the nearend ADC (ADC C in
ACQUISITION
SDO
SDO
CNV = SDI
t
HSCKCNV
A
B
SCK
= SDI
= SDI
SDO
A
B
C
C
SDI
CONVERSION
t
t
DSDOSDI
t
SSCKCNV
t
AD7685
CONV
DSDOSDI
t
EN
CNV
SCK
A
SDO
t
t
t
SSDISCK
HSDO
DSDO
1
D
D
D
C
A
B
2
15 D
15 D
15 D
Figure 45. Chain Mode with BUSY Indicator Serial Interface Timing
Figure 44. Chain Mode with BUSY Indicator Connection Diagram
C
3
A
B
14 D
14 D
14 D
t
SDI
SCKH
C
A
B
4
t
HSDISCK
13
13
13
AD7685
CNV
SCK
B
15
t
SCK
Rev. B | Page 23 of 28
D
D
D
SDO
16
C
B
A
1
1
1
t
SCKL
D
D
D
17
C
A
B
0
0 D
0
D
ACQUISITION
18
B
A
15 D
15 D
t
CYC
Figure 44) SDO is driven high. This transition on SDO can be
used as a BUSY indicator to trigger the data readback controlled
by the digital host. The AD7685 then enters the acquisition
phase and powers down. The data bits stored in the internal
shift register are then clocked out, MSB first, by subsequent
SCK falling edges. For each ADC, SDI feeds the input of the
internal shift register and is clocked by the SCK falling edge.
Each ADC in the chain outputs its data MSB first, and 16 × N + 1
clocks are required to readback the N ADCs. Although the
rising edge can be used to capture the data, a digital host also
using the SCK falling edge allows a faster reading rate and,
consequently, more AD7685s in the chain, provided the digital
host has an acceptable hold time. For instance, with a 5 ns
digital host setup time and 3 V interface, up to eight AD7685s
running at a conversion rate of 220 kSPS can be daisy-chained
to a single 3-wire port.
19
B
SDI
A
t
14
14
ACQ
AD7685
CNV
SCK
31
C
D
D
32
B
A
SDO
1
1
D
D
33
B
A
0 D
0
34
A
15
D
35
A
14
CLK
CONVERT
DATA IN
IRQ
DIGITAL HOST
47
t
DSDOSDI
D
48
t
A
DSDOSDI
t
1
DSDOSDI
D
49
A
0
AD7685