HI5746KCA Intersil, HI5746KCA Datasheet - Page 13

IC ADC 10-BIT 40MSPS 28-SSOP

HI5746KCA

Manufacturer Part Number
HI5746KCA
Description
IC ADC 10-BIT 40MSPS 28-SSOP
Manufacturer
Intersil
Datasheet

Specifications of HI5746KCA

Number Of Bits
10
Sampling Rate (per Second)
40M
Data Interface
Parallel
Number Of Converters
8
Power Dissipation (max)
275mW
Voltage Supply Source
Analog and Digital
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
28-SSOP (0.150", 3.95mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
HI5746KCA
Manufacturer:
Intersil
Quantity:
86
at positive full scale when the V
V
negative fullscale when the V
The analog input can be DC coupled (Figure 27) as long as
the inputs are within the analog input common mode voltage
range (0.25V ≤ VDC ≤ 4.75V).
The resistors, R, in Figure 27 are not absolutely necessary
but may be used as load setting resistors. A capacitor, C,
connected from V
frequency noise on the inputs, also improving performance.
Values around 20pF are sufficient and can be used on AC
coupled inputs as well. Note, however, that the value of
capacitor C chosen must take into account the highest
frequency component of the analog input signal.
Analog Input, Single-Ended Connection
The configuration shown in Figure 28 may be used with a
single ended AC coupled input.
Again, assume the difference between V
and V
then V
equal to VDC . The converter will be at positive full scale
when V
be at negative full scale when V
VDC - 0.5V (V
be provided such that the input voltage never goes above
+5V or below AGND. In this case, VDC could range between
0.5V and 4.5V without a significant change in ADC
performance. The simplest way to produce VDC is to use the
DC bias source, V
V
0.25V and V
DC
IN
- = +0.5V). Conversely, the converter will be at
V
V
+ 0.25V and the V
V
DC
DC
REF
IN
FIGURE 28. AC COUPLED SINGLE ENDED INPUT
IN
FIGURE 27. DC COUPLED DIFFERENTIAL INPUT
IN
+ is a 1V
+ is at VDC + 0.5V (V
-, typically 2V, is 0.5V. If V
V
IN
-V
IN
IN
IN
V
- is at V
DC
+ - V
P-P
IN
DC
+ to V
, output of the HI5746.
sinewave riding on a positive voltage
IN
- = -0.5V). Sufficient headroom must
DC
IN
IN
- input is at V
+ 0.25V (V
- will help filter any high
13
R
R
IN
R
IN
IN
+ input is equal to V
IN
+ - V
+ is equal to
+ input is at
IN
C
is a 1V
IN
IN
REF
DC
- = +0.5V) and will
+ - V
V
V
V
V
V
DC
IN
IN
- 0.25V (V
IN
IN
+, typically 2.5V,
-
+
HI5746
HI5746
-
P-P
+
IN
- = -0.5V).
sinewave,
DC
IN
+ -
-
HI5746
The single ended analog input can be DC coupled
(Figure 27) as long as the input is within the analog input
common mode voltage range.
The resistor, R, in Figure 29 is not absolutely necessary but
may be used as a load setting resistor. A capacitor, C,
connected from V
frequency noise on the inputs, also improving performance.
Values around 20pF are sufficient and can be used on AC
coupled inputs as well. Note, however, that the value of
capacitor C chosen must take into account the highest
frequency component of the analog input signal.
A single ended source may give better overall system
performance if it is first converted to differential before
driving the HI5746.
Digital Output Control and Clock Requirements
The HI5746 provides a standard high-speed interface to
external TTL logic families.
In order to ensure rated performance of the HI5746, the duty
cycle of the clock should be held at 50% ±5%. It must also
have low jitter and operate at standard TTL levels.
Performance of the HI5746 will only be guaranteed at
conversion rates above 1 MSPS. This ensures proper
performance of the internal dynamic circuits. Similarly, when
power is first applied to the converter, a maximum of 20
cycles at a sample rate above 1 MSPS will have to be
performed before valid data is available.
A Data Format Select (DFS) pin is provided which will
determine the format of the digital data outputs. When at
logic low, the data will be output in offset binary format.
When at logic high, the data will be output in two’s
complement format. Refer to Table 1 for further information.
FIGURE 29. DC COUPLED SINGLE ENDED INPUT
V
DC
V
IN
V
DC
IN
+ to V
IN
- will help filter any high
R
C
V
V
IN
IN
-
HI5746
+

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