MCP4161-502E/SN Microchip Technology, MCP4161-502E/SN Datasheet - Page 41

• Manufacturer Part Number: MCP4161-502E/SN
• Description: IC POT DGTL SNGL 5K SPI 8SOIC
• Manufacturer: Microchip Technology

Specifications of MCP4161-502E/SN

• Package / Case: 8-SOIC (3.9mm Width)
• Taps: 257
• Resistance (ohms): 5K
• Number Of Circuits: 1
• Temperature Coefficient: 150 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: SPI Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Resistance In Ohms: 5K
• Number Of Pots: Single
• Taps Per Pot: 256
• Resistance: 5 KOhms
• Wiper Memory: Non Volatile
• Digital Interface: Serial (4-Wire, SPI)
• Operating Supply Voltage: 2.5 V, 3.3 V, 5 V
• Supply Current: 550 uA
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

6.1.4
The SPI interface is specified to operate up to 10 MHz.
The actual clock rate depends on the configuration of
the system and the serial command used.
shows the SCK frequency for different configurations.
TABLE 6-1:
© 2008 Microchip Technology Inc.
Non-Volatile
Memory
Volatile
Memory
Memory Type Access
Note 1: MCP41X1 devices only
2: Non-Volatile memory does not support
3: After a Write command, the internal write
4: This is the maximum clock frequency
SERIAL CLOCK (SCK)
(SPI FREQUENCY OF OPERATION)
the Increment or Decrement command.
cycle must complete before the next SPI
command is received.
without an external pull-up resistor.
SDI, SDO
SDI, SDO
SDI/SDO
SDI/SDO
SCK FREQUENCY
(1)
(1)
250 kHz
250 kHz
10 MHz
10 MHz
Read
Command
(4)
(4)
10 MHz
10 MHz
Increment,
Decrement
10 MHz
10 MHz
Write,
Table 6-1
MCP414X/416X/424X/426X
(2, 3)
(2, 3)
6.1.5
The Chip Select (CS) signal is used to select the device
and frame a command sequence. To start a command,
or sequence of commands, the CS signal must
transition from the inactive state (V
(V
After the CS signal has gone active, the SDO pin is
driven and the clock bit counter is reset.
If an error condition occurs for an SPI command, then
the Command byte’s Command Error (CMDERR) bit
(on the SDO pin) will be driven low (V
error condition, the user must take the CS pin to the V
level.
When the CS pin returns to the inactive state (V
SPI module resets (including the address pointer).
While the CS pin is in the inactive state (V
interface is ignored. This allows the Host Controller to
interface to other SPI devices using the same SDI,
SDO, and SCK signals.
The CS pin has an internal pull-up resistor. The resistor
is disabled when the voltage on the CS pin is at the V
level. This means that when the CS pin is not driven,
the internal pull-up resistor will pull this signal to the V
level.
resistance becomes very large to reduce the device
current consumption.
The high voltage capability of the CS pin allows High
Voltage commands. High Voltage commands allow the
device’s WiperLock Technology and write protect
features to be enabled and disabled.
IL
Note:
or V
When the CS pin is driven low (V
IHH
).
THE CS SIGNAL
There is a required delay after the CS pin
goes active to the 1st edge of the SCK pin.
IH
) to an active state
DS22059B-page 41
IL
). To exit the
IH
), the serial
IL
IH
), the
) the
IH
IH
IL