MCP4161-502E/SN Microchip Technology, MCP4161-502E/SN Datasheet - Page 61

• Manufacturer Part Number: MCP4161-502E/SN
• Description: IC POT DGTL SNGL 5K SPI 8SOIC
• Manufacturer: Microchip Technology

Specifications of MCP4161-502E/SN

• Package / Case: 8-SOIC (3.9mm Width)
• Taps: 257
• Resistance (ohms): 5K
• Number Of Circuits: 1
• Temperature Coefficient: 150 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: SPI Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Resistance In Ohms: 5K
• Number Of Pots: Single
• Taps Per Pot: 256
• Resistance: 5 KOhms
• Wiper Memory: Non Volatile
• Digital Interface: Serial (4-Wire, SPI)
• Operating Supply Voltage: 2.5 V, 3.3 V, 5 V
• Supply Current: 550 uA
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.8 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

8.4
In the design of a system with the MCP4XXX devices,
the following considerations should be taken into
account:
•
•
8.4.1
The typical application will require a bypass capacitor
in order to filter high-frequency noise, which can be
induced onto the power supply's traces. The bypass
capacitor helps to minimize the effect of these noise
sources on signal integrity.
appropriate bypass strategy.
In this example, the recommended bypass capacitor
value is 0.1 µF. This capacitor should be placed as
close (within 4 mm) to the device power pin (V
possible.
The power source supplying these devices should be
as clean as possible. If the application circuit has
separate digital and analog power supplies, V
V
FIGURE 8-6:
Connections.
© 2008 Microchip Technology Inc.
SS
Power Supply Considerations
Layout Considerations
should reside on the analog plane.
W
A
B
Design Considerations
POWER SUPPLY
CONSIDERATIONS
0.1 µF
V
V
Typical Microcontroller
DD
SS
Figure 8-6
0.1 µF
U/D
CS
illustrates an
V
V
DD
SS
DD
DD
MCP414X/416X/424X/426X
) as
and
8.4.2
Inductively-coupled AC transients and digital switching
noise can degrade the input and output signal integrity,
potentially masking the MCP4XXX’s performance.
Careful board layout minimizes these effects and
increases the Signal-to-Noise Ratio (SNR). Multi-layer
boards utilizing a low-inductance ground plane,
isolated inputs, isolated outputs and proper decoupling
are critical to achieving the performance that the silicon
is capable of providing. Particularly harsh environ-
ments may require shielding of critical signals.
If low noise is desired, breadboards and wire-wrapped
boards are not recommended.
8.4.3
Characterization curves of the resistor temperature
coefficient
Figure
These curves show that the resistor network is
designed to correct for the change in resistance as
temperature increases. This technique reduces the
end to end change is R
8.4.4
High Voltage support (V
supports two features. These are:
• In-Circuit Accommodation of split rail applications
• User configuration of the Non-Volatile EEPROM,
and power supply sync issues
Write Protect, and WiperLock feature
Note:
2-19,
LAYOUT CONSIDERATIONS
RESISTOR TEMPCO
HIGH VOLTAGE TOLERANT PINS
In many applications, the High Voltage will
only be present at the manufacturing
stage so as to “lock” the Non-Volatile wiper
value (after calibration) and the contents
of the EEPROM. This ensures that the
since High Voltage is not present under
normal operating conditions, that these
values can not be modified.
(Tempco)
Figure
2-29, and
AB
IHH
are
resistance.
) on the Serial Interface pins
Figure
shown
DS22059B-page 61
2-39.
in
Figure
2-8,