ISL22313UFU10Z Intersil, ISL22313UFU10Z Datasheet - Page 11

• Manufacturer Part Number: ISL22313UFU10Z
• Description: IC POT DGTL 256TP LN LP 10-MSOP
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of ISL22313UFU10Z

• Taps: 256
• Resistance (ohms): 50K
• Number Of Circuits: 1
• Temperature Coefficient: 50 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.25 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Resistance In Ohms: 50K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Device Address (A1, A0)
The address inputs are used to set the least significant 2 bits
of the 7-bit I
address serial data stream must match with the Address
input pins in order to initiate communication with the
ISL22313. A maximum of four ISL22313 devices may
occupy the I
Principles of Operation
The ISL22313 is an integrated circuit incorporating one DCP
with its associated registers, non-volatile memory and an I
serial interface providing direct communication between a
host and the potentiometer and memory. The resistor array
is comprised of individual resistors connected in series. At
either end of the array and between each resistor is an
electronic switch that transfers the potential at that point to
the wiper.
The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions.
When the device is powered down, the last value stored in
IVR will be maintained in the non-volatile memory. When
power is restored, the contents of the IVR are recalled and
loaded into the WR to set the wiper to the initial value.
DCP Description
The DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (RH and RL pins). The RW pin of the DCP is
connected to intermediate nodes, and is equivalent to the
wiper terminal of a mechanical potentiometer. The position
of the wiper terminal within the DCP is controlled by an 8-bit
volatile Wiper Register (WR). When the WR of a DCP
contains all zeroes (WR[7:0]= 00h), its wiper terminal (RW)
is closest to its “Low” terminal (RL). When the WR register of
a DCP contains all ones (WR[7:0]= FFh), its wiper terminal
(RW) is closest to its “High” terminal (RH). As the value of
the WR increases from all zeroes (0) to all ones (255
decimal), the wiper moves monotonically from the position
closest to RL to the position closest to RH. At the same time,
the resistance between RW and RL increases monotonically,
while the resistance between RH and RW decreases
monotonically.
While the ISL22313 is being powered up, the WR is reset to
80h (128 decimal), which locates RW roughly at the center
between RL and RH. After the power supply voltage
becomes large enough for reliable non-volatile memory
reading, the WR will be reloaded with the value stored in a
non-volatile Initial Value Register (IVR).
The WR and IVR can be read or written to directly using the
I
2
C serial interface as described in the following sections.
2
2
C interface slave address. A match in the slave
C serial bus (see Table 3).
11
2
C
ISL22313
Memory Description
The ISL22313 contains one non-volatile 8-bit Initial Value
Register (IVR), fourteen General Purpose non-volatile 8-bit
registers and two volatile 8-bit registers: Wiper Register (WR)
and Access Control Register (ACR). Memory map of ISL22313
is in Table 1. The non-volatile register (IVR) at address 0,
contains initial wiper position and volatile register (WR) contains
current wiper position.
The non-volatile IVR and volatile WR registers are
accessible with the same address.
The Access Control Register (ACR) contains information
and control bits described below in Table 2.
The VOL bit (ACR[7]) determines whether the access to
wiper registers WR or initial value registers IVR.
If VOL bit is 0, the non-volatile IVR register is accessible. If
VOL bit is 1, only the volatile WR is accessible. Note: Value
is written to IVR register also is written to the WR. The
default value of this bit is 0.
The SHDN bit (ACR[6]) disables or enables Shutdown mode.
When this bit is 0, i.e. DCP is forced to end-to-end open
circuit and RW is shorted to RL as shown on Figure 15.
Default value of the SHDN bit is 1.
NAME
ADDRESS
BIT #
(hex)
10
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
TABLE 2. ACCESS CONTROL REGISTER (ACR)
VOL
7
SHDN
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
NON-VOLATILE
6
TABLE 1. MEMORY MAP
WIP
N/A
IVR
5
4
0
Reserved
3
0
2
0
VOLATILE
ACR
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
WR
1
0
July 17, 2007
FN6421.0
0
0