AD5170BRM50-RL7 Analog Devices Inc, AD5170BRM50-RL7 Datasheet - Page 5

• Manufacturer Part Number: AD5170BRM50-RL7
• Description: IC DGTL POT 50K 256POS 10MSOP TR
• Manufacturer: Analog Devices Inc

Specifications of AD5170BRM50-RL7

• Rohs Status: RoHS non-compliant
• Taps: 256
• Resistance (ohms): 50K
• Number Of Circuits: 1
• Temperature Coefficient: 35 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Resistance In Ohms: 50K

Parameter
POWER SUPPLIES
DYNAMIC CHARACTERISTICS
1
2
3
4
5
6
7
8
9
10
11
12
13
Typical specifications represent average readings at 25°C and V
Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic.
V
INL and DNL are measured at V
of ±1 LSB maximum are guaranteed monotonic operating conditions.
The A, B, and W resistor terminals have no limitations on polarity with respect to each other.
Guaranteed by design and not subject to production test.
Measured at the A terminal. The A terminal is open circuited in shutdown mode.
The minimum voltage requirement on the V
to V
up resistors.
Different from operating power supply, power supply OTP is used one time only.
Different from operating current, supply current for OTP lasts approximately 400 ms for use one time only.
See Figure 26 for the energy plot during OTP program.
P
All dynamic characteristics use V
AB
Power Supply Range
OTP Supply Voltage
Supply Current
OTP Supply Current
Power Dissipation
Power Supply Sensitivity
–3 dB Bandwidth
Total Harmonic Distortion
V
Resistor Noise Voltage Density
DISS
W
= V
DD
Settling Time (10 kΩ/50 kΩ/100 kΩ)
is calculated from (I
. However, care must be taken to ensure that the minimum V
DD
, wiper (V
W
) = no connect.
12
DD
8, 9
8, 10, 11
× V
DD
W
). CMOS logic level inputs result in minimum power dissipation.
with the RDAC configured as a potentiometer divider similar to a voltage output DAC. V
DD
13
= 5 V.
IH
is 0.7 V × V
DD
. For example, V
Symbol
V
V
I
I
P
PSS
BW
THD
t
e
DD
DD_OTP
DD
S
DISS
N_WB
DD RANGE
DD_OTP
= 5 V.
IH
W
is met when the SCL and SDA are driven directly from a low voltage logic controller without pull-
Rev. F | Page 5 of 24
IH
minimum = 3.5 V when V
Conditions
V
V
V
V
midscale
R
R
R
V
R
V
band
R
AB
IH
DD_OTP
IH
DD
AB
AB
AB
A
A
WB
=1 V rms, V
= 5 V, V
= 5 V or V
= 5 V or V
= 10 kΩ
= 10 kΩ, code = 0x80
= 50 kΩ, code = 0x80
= 100 kΩ, code = 0x80
= 5 V ± 10%, code =
= 5 kΩ, f = 1 kHz
= 5 V, T
B
= 0 V, ±1 LSB error
IL
IL
B
= 0 V
A
= 0 V, V
= 0 V, f = 1 kHz,
= 25°C
DD
= 5 V. It is typical for the SCL and SDA resistors to be pulled up
DD
= 5 V
A
Min
2.7
5.6
= V
DD
and V
Typ
5.7
3.5
100
±0.02
600
100
40
0.1
2
9
B
= 0 V. DNL specification limits
1
Max
5.5
5.8
6
33
±0.08
AD5170
Unit
V
V
μA
mA
μW
%/%
kHz
kHz
kHz
%
μs
nV/√Hz