AD5233BRUZ50-R7 Analog Devices Inc, AD5233BRUZ50-R7 Datasheet - Page 28

• Manufacturer Part Number: AD5233BRUZ50-R7
• Description: IC DGTL POT QUAD 64POS 24-TSSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5233BRUZ50-R7

• Taps: 64
• Resistance (ohms): 50K
• Number Of Circuits: 4
• Temperature Coefficient: 600 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: 4-Wire SPI Serial
• Voltage - Supply: 2.7 V ~ 5.5 V, ±2.25 V ~ 2.75 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-TSSOP
• Resistance In Ohms: 50K
• Number Of Elements: 4
• # Of Taps: 64
• Resistance (max): 50KOhm
• Power Supply Requirement: Single/Dual
• Interface Type: Serial (4-Wire/SPI)
• Single Supply Voltage (typ): 3/5V
• Dual Supply Voltage (typ): ±2.5V
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (min): ±2.25V
• Dual Supply Voltage (max): ±2.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 24
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5233
In voltage divider mode, by paralleling a discrete resistor as
shown in Figure 61, a proportionately lower voltage appears at
Terminal A to Terminal B. This translates into a finer degree of
precision because the step size at Terminal W is smaller.
The voltage can be found as follows:
Figure 60 and Figure 61 show that the digital potentiometer
steps change linearly. On the other hand, log taper adjustment
is usually preferred in applications such as audio control.
Figure 62 shows another type of resistance scaling. In this
configuration, the smaller the R2 with respect to R1, the
more the pseudo log taper characteristic of the circuit behaves.
DOUBLING THE RESOLUTION
Borrowing from Analog Devices’ patented RDAC segmentation
technique, the user can configure three channels of AD5233, as
shown in Figure 63. By paralleling a discrete resistor, R
R
AD5233 from 6 bits to 12 bits. One might think that moving
RDAC1 and RDAC2 together would form the coarse 6-bit
resolution, and then moving RDAC3 would form the finer
6-bit resolution. As a result, the effective resolution would
become 12 bits. However, the precision of this circuit remains
only 6-bit accurate and the programming can be complicated.
AB
Figure 62. Resistor Scaling with Pseudo Log Adjustment Characteristics
/64), with RDAC3, the user can double the resolution of
V
W
(
D
)
Figure 63. Doubling AD5233 from 6 Bits to 12 Bits
=
Figure 61. Lowering the Nominal Resistance
R
(
3
R
+
AB
RDAC1
RDAC2
R
AB
||
R2
A1
B1
A2
B2
R
R1
||
2
A
B
V
R
)
V
A
2
i
R
×
P
W
64
D
R3
R1
R2
A
B
V
×
DD
V
0
DD
RDAC3
A3
B3
W
V
O
W3
P
( R
P
=
(19)
Rev. B | Page 28 of 32
RESISTANCE TOLERANCE, DRIFT, AND
TEMPERATURE MISMATCH CONSIDERATIONS
In a rheostat mode operation such as gain control (see Figure 64),
the tolerance mismatch between the digital potentiometer and
the discrete resistor can cause repeatability issues among various
systems. Because of the inherent matching of the silicon process,
it is practical to apply the dual- or multiple-channel device in
this type of application. As such, R1 can be replaced by one of
the channels of the digital potentiometer and programmed to a
specific value. R2 can be used for the adjustable gain. Although
it adds cost, this approach minimizes the tolerance and
temperature coefficient mismatch between R1 and R2. This
approach also tracks the resistance drift over time. As a result,
all nonideal parameters become less sensitive to the system
variations.
RDAC CIRCUIT SIMULATION MODEL
The internal parasitic capacitances and the external load
dominate the ac characteristics of the RDACs. Configured as
a potentiometer divider, the −3 dB bandwidth of the AD5233
(10 kΩ resistor) measures 370 kHz at half scale. Figure 14
provides the large signal bode plot characteristics. A parasitic
simulation model is shown in Figure 65.
The following code provides a macromodel net list for the
10 kΩ RDAC:
Listing I. spice model net list
.PARAM D = 64, RDAC = 10E3
*
.SUBCKT DPOT (A, W, B)
*
CA
RWA
CW
RWB
CB
*
.ENDS DPOT
Figure 64. Linear Gain Control with Tracking Resistance Tolerance
A
A
W
W
B
Figure 65. RDAC Circuit Simulation Model for RDAC = 10 kΩ
0
W
0
B
0
35E-12
{(1-D/64)* RDAC + 15}
35-12
{D/64 * RDAC + 15}
35E-12
A
35pF
*REPLACED WITH ANOTHER
CHANNEL OF RDAC
R1*
C
and Temperature Coefficient
A
V
i
RDAC
10kΩ
+
–
AD8601
B
W
W
C1
R2
35pF
U1
C
A
W
C
35pF
B
V
B
O