X9259US24Z Intersil, X9259US24Z Datasheet - Page 9

• Manufacturer Part Number: X9259US24Z
• Description: IC XDCP QUAD 256TAP 50K 24-SOIC
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of X9259US24Z

• Taps: 256
• Resistance (ohms): 50K
• Number Of Circuits: 4
• Temperature Coefficient: 300 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (7.5mm Width)
• Resistance In Ohms: 50K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Instructions
Four of the nine instructions are three bytes in length. These
instructions are:
• Read Wiper Counter Register – read the current wiper
• Write Wiper Counter Register – change current wiper
• Read Data Register – read the contents of the selected
• Write Data Register – write a new value to the selected
The basic sequence of the three byte instructions is
illustrated in Figure 5. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the wiper to
this action is delayed by t
(current wiper position), to a Data Register is a write to non-
volatile memory and takes a minimum of t
The transfer can occur between one of the four
potentiometer’s WCR, and one of its associated registers,
DRs; or it may occur globally, where the transfer occurs
between all potentiometers and one associated register.
Four instructions require a two-byte sequence to complete.
These instructions transfer data between the host and the
X9259; either between the host and one of the data registers
SCL
SDA
position of the selected potentiometer,
position of the selected potentiometer,
Data Register;
Data Register.
S
T
A
R
T
ID3 ID2 ID1 ID0
0
Device ID
SCL
SDA
1
0
S
T
A
R
T
1
ID3 ID2 ID1 ID0
WRL
0
A3
. A transfer from the WCR
Device ID
1
9
FIGURE 5. THREE-BYTE INSTRUCTION SEQUENCE 2-WIRE INTERFACE
A2
0
External
Address
A1
1
A3
A0 A
FIGURE 4. TWO-BYTE INSTRUCTION SEQUENCE
WR
C
K
A2
to complete.
External
Address
I3
A1
Instruction
Opcode
I2
A0
I1 I0
A
C
K
X9259
I3
Instruction
Opcode
RB RA
Register
Address
I2
I1
or directly between the host and the Wiper Counter Register.
These instructions are:
• XFR Data Register to Wiper Counter Register – This
• XFR Wiper Counter Register to Data Register – This
• Global XFR Data Register to Wiper Counter
• Global XFR Wiper Counter Register to Data
Increment/Decrement Command
The final command is Increment/Decrement (Figure 6 and
7). The Increment/Decrement command is different from the
other commands. Once the command is issued and the
X9259 has responded with an Acknowledge, the master can
clock the selected wiper up and/or down in one segment
steps; thereby, providing a fine tuning capability to the host.
For each SCL clock pulse (t
selected wiper moves one wiper position towards the R
terminal. Similarly, for each SCL clock pulse while SDA is
LOW, the selected wiper moves one resistor wiper position
towards the R
See Instruction format for more details.
transfers the contents of one specified Data Register to
the associated Wiper Counter Register.
transfers the contents of the specified Wiper Counter
Register to the specified associated Data Register.
Register – This transfers the contents of all specified Data
Registers to the associated Wiper Counter Registers.
Register – This transfers the contents of all Wiper
Counter Registers to the specified associated Data
Registers.
I0
Address
P1 P0 A
Pot/WCR
Register
Address
RB RA P1
C
K
L
terminal.
D7 D6 D5 D4 D3 D2 D1 D0
DCP/WCR
Address
Data for WCR[7:0] or DR[7:0]
P0
A
C
K
HIGH
S
T
O
P
) while SDA is HIGH, the
A
C
K
April 13, 2007
S
T
O
P
FN8169.5
H