MPC8309VMAHFCA Freescale Semiconductor, MPC8309VMAHFCA Datasheet - Page 13

• Manufacturer Part Number: MPC8309VMAHFCA
• Description: 417/333/233 MP Std Tmp
• Manufacturer: Freescale Semiconductor

Specifications of MPC8309VMAHFCA

• Processor Series: MPC8309
• Core: e300c3
• Data Bus Width: 32 bit
• Data Ram Size: 512 MB
• Interface Type: USB, CAN, UART, PCI
• Maximum Clock Frequency: 417 MHz
• Number Of Programmable I/os: 56
• Operating Supply Voltage: - 0.3 V to + 1.26 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Operating Temperature Range: 0 C to + 105 C
• Processor To Be Evaluated: MPC8309
• Supply Current (max): 5 uA
• Lead Free Status / Rohs Status: Details

4.2
The primary clock source for the MPC8309 can be one of two inputs, SYS_CLK_IN or PCI_SYNC_IN,
depending on whether the device is configured in PCI host or agent mode. The following table provides
the clock input (SYS_CLK_IN/PCI_SYNC_IN) AC timing specifications for the MPC8309. These
specifications are also applicable for QE_CLK_IN.
5
This section describes the AC electrical specifications for the reset initialization timing requirements of
the MPC8309. The following table provides the reset initialization AC timing specifications for the reset
component(s).
Freescale Semiconductor
SYS_CLK_IN frequency
SYS_CLK_IN cycle time
SYS_CLK_IN rise and fall time
PCI_SYNC_IN rise and fall time
SYS_CLK_IN duty cycle
SYS_CLK_IN jitter
Notes:
1. Caution: The system, core and QUICC Engine block must not exceed their respective maximum or minimum operating
2. Rise and fall times for SYS_CLK_IN are measured at 0.33 and 2.97 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter—short term and long term—and is guaranteed by design.
5. The SYS_CLK_IN driver’s closed loop jitter bandwidth should be < 500 kHz at –20 dB. The bandwidth must be set low to
6. Spread spectrum is allowed up to 1% down-spread @ 33kHz (max rate).
Required assertion time of HRESET to activate reset flow
Required assertion time of PORESET with stable clock applied to
SYS_CLK_IN or PCI_SYNC_IN (in agent mode)
HRESET assertion (output)
frequencies.
allow cascade-connected PLL-based devices to track SYS_CLK_IN drivers with the specified jitter.
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 1
RESET Initialization
AC Electrical Characteristics
Parameter/Condition
Parameter/Condition
Table 9. RESET Initialization Timing Specifications
Table 8. SYS_CLK_IN AC Timing Specifications
t
KHK
f
t
SYS_CLK_IN
SYS_CLK_IN
t
PCH
Symbol
t
KH
/t
SYS_CLK_
—
IN
, t
, t
KL
PCL
Min
1.1
1.1
24
15
40
—
Min
512
32
32
Typical
—
—
—
—
—
—
Max
—
—
—
66.67
±150
Max
41.6
2.8
2.8
60
t
t
t
SYS_CLK_IN
SYS_CLK_IN
SYS_CLK_IN
Unit
RESET Initialization
Unit
MHz
ns
ns
ns
ps
%
Note
Note
4, 5
—
1
2
2
3
1
1
1
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